• Nuclear Engineering and Technology
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• v.56 no.5
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• pp.1654-1666
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• 2024

The goal of this research is to propose a way to maximize small modular reactor (SMR) utilization to gain better market feasibility in support of carbon neutrality. For that purpose, a comprehensive tool was developed, combining off-design thermohydraulic models, economic objective models (levelized cost of electricity, annual profit), non-economic models (saved CO2), a parameter input sampling method (Latin hypercube sampling, LHS), and a multi-objective evolutionary algorithm (Non-dominated Sorting Algorithm-2, NSGA2 method) for optimizing a SMR-combined heat and power cycle (CHP) system design. Considering multiple objectives, it was shown that NSGA2+LHS method can find better optimal solution sets with similar computational costs compared to a conventional weighted sum (WS) method. Out of multiple multi-objective optimal design configurations for a 105 MWe design generation rating, a chosen reference SMR-CHP system resulted in its levelized cost of electricity (LCOE) below $60/MWh for various heat prices, showing economic competitiveness for energy market conditions similar to South Korea. Examined economic feasibility may vary significantly based on CHP heat prices, and extensive consideration of the regional heat market may be required for SMR-CHP regional optimization. Nonetheless, with reasonable heat market prices (e.g. district heating prices comparable to those in Europe and Korea), SMR can still become highly competitive in the energy market if coupled with a CHP system.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.51 no.2
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• pp.163-170
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• 2015

Recently LED fish-attracting lamps have been more widely used in fisheries as low-cost and high-efficiency fishing gear, and development of long-life high-efficiency lamps is required through the design of LED packages to optimize heat resistance. This study developed an improved LED fish-attracting lamp with excellent heat performance, which was verified using a numerical model. Heat-resistance design factors such as the heat-radiation fin shape, PCB type, and LED chip count were investigated and optimized. Comparison with a commercial 180-W LED fishing lamp showed that the increase in initial temperature was 40% higher than that of the surrounding LED chip because of design errors in contact thermal resistance. The 250-W LED lamp developed in this study has a characteristic with thermal rising in linearly stable according to the heat source. In addition, luminance efficiency was improved by 20-65% by using flow-visualization simulation. A decrease of 45% in total power consumption with a fuel-cost reduction of over 55% can be expected when using these optimized heat release design factors.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.115-121
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• 2006

The efficiency of the multiplier largely depends on the representation of finite filed elements such as normal basis, polynomial basis, dual basis, and redundant representation, and so on. In particular, the redundant representation is attractive since it can simply implement squaring and modular reduction. In this paper, we propose an efficient bit-parallel multiplier for GF(2m) defined by an irreducible all-one polynomial using a redundant representation. We modify the well-known multiplication method which was proposed by Karatsuba to improve the efficiency of the proposed bit-parallel multiplier. As a result, the proposed multiplier has a lower space complexity compared to the previously known multipliers using all-one polynomials. On the other hand, its time complexity is similar to the previously proposed ones.

• The KIPS Transactions:PartC
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• v.17C no.2
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• pp.145-152
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• 2010

In this paper, we first propose a fast division algorithm in GF($2^{163}$) using standard basis representation, and then it is mapped into divider for GF($2^{163}$) with iterative hardware structure. The proposed algorithm is based on the binary ExtendedGCD algorithm, and the arithmetic operations for modular reduction are performed within only one "while-statement" unlike conventional approach which uses two "while-statement". In this paper, we use reduction polynomial $f(x)=x^{163}+x^7+x^6+x^3+1$ that is recommended in SEC2(Standards for Efficient Cryptography) using standard basis representation, where degree m = 163. We also have implemented the proposed iterative architecture in FPGA using Verilog HDL, and it operates at a clock frequency of 85 MHz on Xilinx-VirtexII XC2V8000 FPGA device. From implementation results, we will show that computation speed of the proposed scheme is significantly improved than the existing two approaches.

• Journal of Power Electronics
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• v.12 no.1
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• pp.24-32
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• 2012

Direct duty-ratio PWM schemes for continuous fault tolerant operation of matrix converter-fed motor drives are presented. The proposed method features simple modular modulation structure based on per output phase concept, which requires no additional modification on the normal modulation schemes for fault-tolerant applications. Realizations of fault-tolerant strategy applied to different system configurations are also treated to enhance the system flexibility. The proposed method can be effectively applied to treat the motor open phase fault and converter switching device failure. Simulation and experimental results show the feasibility and validation of the proposed strategies.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.7 no.1
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• pp.7-16
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• 2007

First, we investigate fuzzy equivalence relations on a set X in the sense of Youssef and Dib. Second, we discuss fuzzy congruences generated by a given fuzzy relation on a fuzzy groupoid. In particular, we obtain the characterizations of ${\rho}\;o\;{\sigma}{\in}$ FC(S) for any two fuzzy congruences ${\rho}\;and\;{\sigma}$ on a fuzzy groupoid ($S,{\odot}$). Finally, we study the lattice of fuzzy equivalence relations (congruences) on a fuzzy semigroup and give certain lattice theoretic properties.

• Journal of Power Electronics
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• v.9 no.4
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• pp.535-543
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• 2009

In this paper, pulse-width modulation (PWM) control strategy of various topologies of matrix converters is presented, which is based on direct duty ratio PWM (DDPWM). Because the DDPWM method has the characteristics of the inherent per-phase modular structure, it can be effectively applied to single-phase, two-phase and three-phase four-leg matrix converters as well as the common three-phase to three-phase matrix converter. Also, this paper treats command generation method in each matrix converter. The feasibility and validity of the proposed method are verified by experimental results.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.48-55
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• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.

• Asian-Australasian Journal of Animal Sciences
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• v.24 no.7
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• pp.1019-1025
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• 2011

Toll-like receptors (TLRs) play an important role in the recognition of invading pathogens and the modulation of innate immune responses in mammals. The TLR4 and TLR7 are well known to recognize the bacterial lipopolysaccharide (LPS) and single stranded (ssRNA) ligands, respectively and play important role in host defense against Gram-negative bacteria and ssRNA viruses. In the present study, coding exon fragments of these two TLRs were identified, cloned, sequenced and analyzed in terms of insertion-deletion polymorphism, within bovine TLRs 4 and 7, thereby facilitating future TLR signaling and association studies relevant to bovine innate immunity. Comparative sequence analysis of TLR 4 exons revealed that this gene is more variable, particularly the coding frame (E3P1), while other parts showed percent identity of 95.7% to 100% at nucleotide and amino acid level, respectivley with other Bos indicus and Bos taurus breeds from different parts of the world. In comparison to TLR4, sequence analysis of TLR7 showed more conservation among different B. indicus and B. taurus breeds, except single point mutation at 324 nucleotide position (AAA to AAM) altering a single amino acid at 108 position (K to X). Percent identity of TLR7 sequences (all 3 exons) was between 99.2% to 100% at nucleotide and amino acid level, when compared with available sequence database of B. indicus and B. taurus. Simple Modular Architecture Research Tool (SMART) analysis showed variations in the exon fragments located in the Leucine Rich Repeat (LRR) region, which is responsible for binding with the microbial associated molecular patterns and further, downstream signaling to initiate anti-microbial response. Considering importance of TLR polymorphism in terms of innate immunity, further research is warranted.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.564-581
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• 2016

We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.