• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.289-292
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• 2007

The modular line-connected photovoltaic PCS (power conditioning system) is proposed. The proposed system consists of a step-up DC-DC converter and a full-bridge inverter. A step-up DC-DC converter using a dual series-resonant rectifier circuit and a active-clamp circuit is proposed to achieve a high efficiency and a high input-output voltage ratio efficiently. An IncCond (incremental conductance) MPPT (maximum power point tracking) algorithm that improves MPPT characteristic is used. By control a inverter using a linearized output current controller, a unity power factor is achieved. All algorithms and controllers are implemented on a single-chip microcontroller and the superiority of the proposed algorithms and controllers is proved by experiments.

• Proceedings of the KIPE Conference
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• 2019.11a
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• pp.140-141
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• 2019

This paper proposes a series operation algorithm for voltage balancing of modular battery pack charging/discharging system using 3P-CFDAB (3-Phase Current-Fed Dual Active Bridge) converter. By using the proposed algorithm, we can prevent deterioration or loss of a particular module. The algorithm in this paper was verified through PSIM simulation.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.3
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• pp.354-359
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• 2012

A transformerless converter suitable for multiphase drive application is presented in this paper. The topology employs a cascaded H-bridge rectifier as the interface between the grid and multi inverters which drive the multiphase motor. Compared with the conventional structure, the new topology eliminates the input transformer and also has the advantages such as four quadrant operation, simple configuration, low cost, high efficiency, and so on. The control strategies for the grid-side cascade H-bridge rectifier and the motor-side inverter are studied accordingly. Based on the multi-rotational reference frame, modular control scheme is developed to regulate the multiphase drive system. Simulation results show the proper operation of the proposed topology and the corresponding control strategy.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.284-287
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• 2001

In the System-integrated modular advanced reactor(SMART), the motor for Control element drive mechanism(CEDM) requires high density power and simple drive mechanism to reduce volume because of restriction by install-space and must satisfy the reactor operating circumstances with high pressure and temperature. To Maximize the characteristics of the TFM, we chose the asymmetric bridge converter as the driving system for TFM. Because two switching devices are connected in series with the stator winding of each phases in the asymmetric bridge converter all the phases are not affected by another phase but controlled independently. Also, this converter has many advantages that the various control methods can be adopted, it is easy to control, and that in case that the switching devices of a phase are damaged, the affects can be minimized.

• Journal of Power Electronics
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• v.12 no.1
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• pp.83-87
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• 2012

Input-series-output-parallel (ISOP) modular converters consisting of multiple modular DC/DC converters can enable low voltage rating switches for use in high voltage input applications. In this paper, an input voltage sharing control strategy for input-series-output-parallel (ISOP) full-bridge (FB) DC/DC converters is proposed. By sensing the difference in the input current of two modules, the system can achieve input voltage sharing for DC-DC modules. The effectiveness of the proposed control strategy is verified by simulation and experimental results obtained with a 200w-50kHz prototype.

• New & Renewable Energy
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• v.1 no.2 s.2
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• pp.11-18
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• 2005

A modular photovoltaic PCS with high-frequency isolation is proposed. The proposed system consists of a SEPIC converter and a full-bridge inverter Using the power slope versus voltage of the PV array, the MPPT controller is proposed that produces a smooth transition to the maximum power point. The dc current of the PV array is estimated without using a dc current sensor The disturbance of the line voltage is detected using a fast sensing technique. Experimental results obtained on a 500W prototype show high performance such as almost unity power factor, $90\%$ power efficiency, $3.6\%$ THD.

• Journal of Power Electronics
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• v.10 no.6
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• pp.673-679
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• 2010

Input-series-output-parallel (ISOP) connected DC-DC converters enable low voltage rating switches to be used in high voltage input applications. In this paper, a DSP is adopted to generate digital phase-shifted PWM signals and to fulfill the closed-loop control function for ISOP connected two full-bridge DC-DC converters. Moreover, a stable output current sharing control strategy is proposed for the system, with which equal sharing of the input voltage and the load current can be achieved without any input voltage control loops. Based on small signal analysis with the state space average method, a loop gain design with the proposed scheme is made. Compared with the conventional IVS scheme, the proposed strategy leads to simplification of the output voltage regulator design and better static and dynamic responses. The effectiveness of the proposed control strategy is verified by the simulation and experimental results of an ISOP system made up of two full-bridge DC-DC converters.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.259-266
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• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1504-1512
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• 2016

This paper presents a new single-phase asymmetrical cascaded multilevel DC-link inverter. The proposed inverter comprises two stages. The main stage of the inverter consists of multiple similar cells, each of which is a half-bridge inverter consisting of two switches and a single DC source. All cells are connected in a cascaded manner with a fixed neutral point. The DC source values are not made equal to increase the performance of the inverter. The second circuit is a folded cascaded H-bridge circuit operating at a line frequency. One of the main advantages of this proposed topology is that it is a modular type and can thus be extended to high stages without changing the configuration of the main stage circuit. Two control schemes, namely, low switching with selective harmonic elimination and sinusoidal pulse width modulation, are employed to validate the proposed topology. The detailed approach of each control scheme and switching pulses are discussed in detail. A 150W prototype of the proposed system is implemented in the laboratory to verify the validity of the proposed topology.

• Journal of IKEEE
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• v.23 no.4
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• pp.1208-1217
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• 2019

The life-cycle prediction of the sub-module which is the unit system of MMC is very important from the viewpoint of maintenance and economic feasibility of HVDC system. However, the life-cycle prediction that considers only the type, number and combination of parts is a generalized result that does not take into account the operating condition of the sub-module, and may significantly differ from the life-cycle of the actual one. Therefore, we design a fault tree for the purpose of reflecting the operation characteristics of the full-bridge sub-module and apply the MIL-HDBK-217F to the failure rate of the basic event to predict the life-cycle of the full-bridge sub-module. It compares the life-cycle expectancy of the conventional failure rate analysis with the proposed fault-tree analysis and compares the lifetime according to whether the redundancy of the full-bridge sub-module is considered.