• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 학술대회 논문집
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• pp.43-46
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• 2003

The dc reactor type high-Tc superconducting fault current limiter(SFCL) is composed of three parts, a power converter, a magnetic core reactor(MCR) and a dc reactor. This study concerned with the power converter of the DC reactor type high-Tc SFCL. The rectifying devices which power converter of 6.6kV/200A SFCL consists of have to endure high voltage. We propose the dual mode power converter to reduce the voltage which each rectifying device endures. In the single phase the experiment and simulation of dual mode power converter and the simulation of power converter with one bridge rectifier are performed. The current of each system with different power converter has a same tendency and the voltage which rectifying device of dual mode power converter endures is reduced in half by comparison with that of power converter with one bridge rectifier. We found dual mode power converter can be applied to SFCL.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.212-216
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• 2001

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitic capacitance between the drain/collector of an active switch and the frame ground through its heat sink may generate the common-mode conducted noise. We have proposed a balanced switching converter circuit, which is an effective way to reduce the common-mode conducted noise. As an example, a boost converter version of the balanced switching converter was presented and the mechanism of the common-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switching converter circuit and presents a buck-boost converter version of the balanced switching converter. The feature of common-mode noise reduction is confirmed by experimental results and the mechanism of the common-mode noise reduction is explained using equivalent circuits.

• Journal of Power Electronics
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• 제2권2호
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• pp.139-145
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• 2002

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitice between the drain/collertor of an active switch and frame ground through its heat sink may generate the commom-mode conducted noise. We have proposed a balanced switching converter circuit, whitch is an effective way to reduce the commom-mode converter version of the balanced switching converter was presented and the mechanism of the commom-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switch converter circuit and presents a buck-boost converter version of the blanced switching converter. The feature of common-mode niose reduction is confirmed by experimental resuits and the mechanisem of the commom-mode niose reduction is explained using equivalent circuits.

• 대한전자공학회논문지SD
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• 제45권6호
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• pp.1-9
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• 2008

본 논문에서는 temperature/voltage에 둔감한 triple-mode CMOS DC-DC Converter를 제안한다. 제안된 triple-mode DC-DC converter는 단일 배터리의 수명에 따른 전압변화(3.3-5.5V)로부터 일정 또는 다양한 출력전압(0.6-2.2V)을 생성한다. 제안된 triple-mode CMOS DC-DC converter는 Pulse Width Modulator(PWM) 모드, Pulse Frequency Modulator(PPM) 모드, 그리고 Low Drop-Out(LDO) 모드, 이렇게 세 가지 모드로 동작한다. 또한, 제안된 회로는 temperature/voltage 변화에 의한 칩의 오동작을 방지하기 위해 temperature/voltage 변화에 둔감한 저 전력 1MHz CMOS ring oscillator를 사용한다. 제안된 triple-mode DC-DC converter는 단일 입력 전원소스(3.3-5.5V)에서 출력 전압(0.6-2.2V)을 생성하며, 출력 전압 ripple은 PWM mode에서 10mv, PFM mode에서 15mV, 그리고 LDO mode에서는 4mV 이하이다. 또한, 제안된 회로의 효율은 PWM mode에서 93% 이상이며, $-25-80^{\circ}C$의 온도변화에도 각 모드에서의 출력 전압 레벨의 오차는 단지 0.8% 이하로 유지한다 제안된 회로의 검증을 위해 CMOS $0.35{\mu}m$ 공정을 이용한 시뮬레이션 및 칩 테스트를 수행하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 전력전자학술대회 논문집
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• pp.337-338
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• 2013

Combination the several type of single phase power conversion utilized simply topology are proposed in this paper. Totally four kind of converter are investigated, they are Boost AC/AC Converter, Buck AC/AC Converter, Boost AC/DC Converter, and Buck DC/AC Converter. Two types action mode are presented to determine the functional of circuit. First is AC chopper action mode, representation of the AC/AC converter. AC chopper action mode offered the sinusoidal current waveform, better power factor, faster dynamics, and smaller input/output filter. They present high robustness, offer safe commutation and have high efficiency. The second is full bridge action mode, determined the transformation AC to DC power and otherwise. Four switching devices and one magnetic contactor will establish the mode operation of circuit and manage the flow of power proceed in proper. The correction and advance of the kind of converter are verified by simulation.

• 한국전자파학회논문지
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• 제19권12호
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• pp.1435-1444
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• 2008

본 논문에서는 짧은 천이길이를 갖는 감소단축도파관(redured-height waveguide) 대 마이크로스트립 모드 변환기(mode converter)를 설계하였다. 모드 변환기는 E-평면 프로브를 이용한 모드 변환기와 변형된 임피던스 변환기로 구성되어진다. E-평면 프로브를 이용한 모드 변환기는 50 ohm 릿지(ridge) 도파관의 릿지 상단에 단락된 프로브를 이용하여 설계하였다. 이 모드 변환기에 이용된 50 ohm 릿지 도파관과 감소단축도파관을 연결하기 위해 변형된 임피던스 변환기를 설계하였다. 이와 같이 구성된 전체 모드 변환기의 대역을 넓히기 위해, 두 구조의 결합도를 조정하였다. 저손실 및 Ku-대역 전체에서 동작하도록 구조를 최적화한 후 모드 변환기를 제작하였다 제작된 2개의 모드 변환기를 직접 연결(thru)한 S-파라미터와 모드 변환기 사이에 라인(line) 도파관을 삽입한 후 S-파라미터를 측정하였다. 측정된 2개의 S-파라미터를 이용하여 단일 모드 변환기의 성능을 추출하였다. 이렇게 추출된 모드 변환기의 성능은 커텍터 손실을 포함하고 있어, 커백터 손실을 측정하여 보상하였다. 모드변환기는 직각구조로 7.2 mm의 천이길이를 가지며, 중심 주파수에서 0.12 dB 삽입 손실과 Ku 전대역에서 10dB 이상의 반사 손실을 갖는 우수한 특성을 보였다.

• 한국광학회지
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• 제15권1호
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• pp.22-27
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• 2004

본 논문에서는 광도파로와 광섬유사이에서 광손실을 줄이기 위한 모드 크기 변환기를 설계하였다. 설계된 모드 크기 변환기는 주기적으로 분리된 테이퍼 광도파로로 구성된 모드 크기 변환기이며, 공정상의 적용이 용이한 수평 테이퍼 구조를 선택하였다. 높이와 폭이 3$\mu\textrm{m}$${\times}$3$\mu\textrm{m}$이며 1.5%실리카 광도파로의 경우 파장이 1550nm 파장에서 최적의 모드 크기 변환기 설계 파라미터는 테이퍼 영역의 길이가 500$\mu\textrm{m}$이고, 분리된 광도파로의 길이는 5$\mu\textrm{m}$이며, 주기의 Duty-Cycle은 0.95, 광도파로와 광섬유의 접속면에서의 폭은 1.3$\mu\textrm{m}$이였다. 이 때 결합손실은 0.33㏈/point로 광섬유와 광도파로를 직접 연결할 때 보다 1.27 ㏈/point가 감소하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.292-300
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• 2015

This paper proposes a high-efficiency, dual-mode PWM / linear buck converter with a wide-input range. The proposed converter was designed with a mode selector that can change the operation between PWM / linear mode by sensing a load current. The proposed converter operates in a linear mode during a light load and in PWM mode during a heavy load condition in order to ensure high efficiency. In addition, the mode selector uses a bit counter and a transmission gate designed to protect from a malfunction due to noise or a time-delay. Also, in conditions between $-40^{\circ}C$ and $140^{\circ}C$, the converter has variations in temperature of $0.5mV/^{\circ}C$ in the PWM mode and of $0.24mV/^{\circ}C$ in the linear mode. Also, to prevent malfunction and breakdown of the IC due to static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class(Chip level) ESD protection circuit of a P-substrate Triggered SCR type with high robustness characteristics.

• Journal of Power Electronics
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• 제9권6호
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• pp.949-959
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• 2009

This paper presents a systematic investigation of the fault-mode behaviors of matrix converter systems. Knowledge about converter behaviors after fault occurrence is important from the standpoint of reliable system design, protection and fault-tolerant control. Converter behaviors have been, in detail, examined with both qualitative and quantitative approaches for key fault types, such as switch open-circuited faults and switch short-circuited faults. Investigating the fault-mode behaviors of matrix converters reveals that converter operation with switch short-circuited faults leads to overvoltage stresses as well as overcurrent stresses on other healthy switching components. On the other hand, switch open-circuited faults only result in overvoltage to other switching components. This study can be used to predict fault-mode converter behaviors and determine additional stresses on remaining power circuit components under fault-mode operations.

• Journal of Power Electronics
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• 제9권1호
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• pp.26-35
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• 2009

A high efficiency active clamp sepic-flyback converter is presented for fuel cell generation systems. The proposed converter is a superposition of a sepic converter mode and. flyback converter mode. The output voltages of the sepic converter mode and flyback converter mode can be regulated by the same PWM technique with constant frequency. By merging the sepic and flyback topologies, they can share the transformer, power MOSFET and active clamp circuit. The result has outstanding advantages over conventional active clamp DC-DC converters: high efficiency, high power density, and component utilization. Simulation results and experimental results are presented to verify the principles of operation for the proposed converter.