• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.443-447
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• 2005

EMAST(Embedded Mobile Automatic System for Telematics) is implemented in SoC using the CAN and ARM Processor. For the general usage, EMAST must satisfy the two condition. First, Mobile internal interface is to be designed to support Differential Transceiver, Optical Transceiver and Wireless Transceiver Second, it should be supporting the interface between terminals using EMAST and telematics networks. In this paper, we propose EMAST structure and the efficient interface structure between EMAST and each mobile units.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.837-840
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• 2005

This paper presents 3D graphics lighting processor based on vector processing using pipeline chaining. The lighting process of 3D graphics rendering contains many arithmetic operations and its complexity is very high. For high throughput, proposed processor uses pipelined functional units. To implement fully pipelined architecture, we have to use many functional units. Hence, the number of functional units is restricted. However, with the restricted number of pipelined functional units, the utilization of the units is reduced and a resource reservation problem is caused. To resolve these problems, the proposed architecture uses vector processing using pipeline chaining. Due to its pipeline chaining based architecture, it can perform 4.09M vertices per 1 second with 100MHz frequency. The proposed 3D graphics lighting processor is compatible with OpenGL ES API and the design is implemented and verified on FPGA.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.66-75
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• 2020

As the increasing expectations of a practical AI (Artificial Intelligence) service makes AI algorithms more complicated, an efficient processor to process AI algorithms is required. To meet this requirement, processors optimized for parallel processing, such as GPUs (Graphics Processing Units), have been widely employed. However, the GPU has a generalized structure for various applications, so it is not optimized for the AI algorithm. Therefore, research on the development of AI processors optimized for AI algorithm processing has been actively conducted. This paper briefly introduces an AI processor especially for inference acceleration, developed by the Electronics and Telecommunications Research Institute, South Korea., and other global vendors for mobile and server platforms. However, the GPU has a generalized structure for various applications, so it is not optimized for the AI algorithm. Therefore, research on the development of AI processors optimized for AI algorithm processing has been actively conducted.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.467-478
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• 2002

With the rapid development of wired or wireless Internet, various kinds of resource constrained mobile devices, such as cellular phone, PDA, homepad, smart phone, handhold PC, and so on, have been emerging into personal or commercial usages. Most software to be embedded into those devices has been forced to have the characteristic of flexibility rather than the fixedness which was an inherent property of embedded system. It means that recent technologies require the flexible embedding into the variety of resource constrained mobile devices. A document processor for XML which has been positioned as a standard mark-up language for information representation on the Web, is one of the essential software to be embedded into those devices for browsing the information. In this paper, a framework for configurable XML processor called EmXJ is designed and implemented for flexible embedding into various types of resource constrained mobile devices, and its advantages are compared to conventional XML processors.

• Electronics and Telecommunications Trends
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• v.28 no.2
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• pp.50-57
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• 2013

스마트폰 및 태블릿 PC에 들어가는 핵심 부품인 AP(Application Processor)는 모두 GPU(Graphics Processing Unit)를 내장하고 있다. 이는 칩 면적의 제약과 사용 가능한 전력의 한계로 데스크톱의 그래픽 카드에 탑재된 고성능 GPU와는 다른 설계 제약을 받는다. 본고에서는 고성능 GPU와 다른 설계 조건을 갖는 mobile GPU 기술에 대해서 알아보았고 대표적인 commercial mobile GPU인 Imagination, ARM, Qualcomm, NVidia사의 mobile GPU의 특징 및 성능에 대해서 알아보았다.

• International Journal of Advanced Culture Technology
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• v.10 no.3
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• pp.360-370
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• 2022

Demand for machine learning systems continues to grow, and cloud machine learning platforms are widely used to meet this demand. Recently, the performance improvement of the application processor of smartphones has become an opportunity for the machine learning platform to move from the cloud to On-Device AI, and mobile applications equipped with machine learning functions are required. In this paper, machine learning tools for mobile applications are investigated and compared the characteristics of these tools.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.137-147
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• 2008

Recently, Power and thermal management are becoming major concerns in computer system design. The energy efficiency is an important attribute of the mobile and embedded systems. Today's powerful mobile processors needs more energy and longer battery life. Many research has been focused to reduce energy consumption for the mobile processors.In this paper, performance monitoring system for the Power-management techniques is implemented for Intel's XScale microarchitecture-based Marvell PXA320 processor on Windows CE platform. It also provides software interface for changing DVFS configuration. Performance and power consumption are measured for benchmark programs through performance counter value and voltage/current measurements on LabVIEW platform. By using the developed monitoring system, it is possible for dynamic power management to track processor's workload and to determine the actual power consumption.

• Journal of the Korea Society of Computer and Information
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• v.15 no.3
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• pp.1-10
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• 2010

As processor platforms are continuously moving toward wireless mobile systems, embedded mobile processors are expected to perform more and more powerful, and therefore the development of an efficient power management algorithm for these battery-operated mobile and handheld systems has become a critical challenge. It is well known that a memory system is a main performance limiter in the processor point of view. Although many DVFS studies have been considered for the efficient utilization of limited battery resources, recent works do not explicitly show the interaction between the processor and the memory. In this research, to properly reflect short/long-term memory access patterns of the embedded workloads in wireless mobile processors, we propose a memory buffer utilization as a new index of DVFS level prediction. The simulation results show that our solution provides 5.86% energy saving compared to the existing DVFS policy in case of memory intensive applications, and it provides 3.60% energy saving on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.