Acknowledgement
This work was supported by the ICT R&D program of MSIT/IITP[2018-0-00195, Artificial Intelligence Processor Research Laboratory].
References
- A. Reuther et al., "Survey and benchmarking of machine learning accelerators," arXiv preprint arXiv:1908.11348, 2019.
- A. Frumusanu, "The Apple iPhone 11, 11 Pro & 11 Pro Max Review: Performance, Battery, & Camera Elevated," Anandtech, Oct. 16, 2019.
- A. Ignatov et al., "AI Benchmark: All About Deep Learning on Smartphones in 2019," arXiv preprint arXiv:1910.06663, 2019.
- Huawei, consumer.huawei.com/en/campaign/kirin-990-series/
- H. Liao, "DaVinci: A Scalable Architecture for Neural Network Computing," 2018, www.hotchips.org/hc31/HC31_1.11_Huawei.Davinci.HengLiao_v4.0.pdf
- Samsung, www.samsung.com/semiconductor/minisite/exynos/products/mobileprocessor/exynos-990/
- S. Windsor, "Snapdragon 865 vs Kirin 990 5G vs Exynos 990 (Exynos 9830) vs MediaTek Dimensity 1000 (MT6889): which one is the best 5G processor?" www.gearbest.com, Dec. 10, 2019.
- H. Liao et al., "DaVinci: A Scalable Architecture for Neural Network Computing," in Proc. Hot Chips 31 Symp., Cupertino, CA, USA, Aug. 18-20, 2019, doi: 10.1109/HOTCHIPS.2019.8875654.
- J. Song et al., "7.1 An 11.5 TOPS/W 1024-MAC butterfly structure dual-core sparsity-aware neural processing unit in 8nm flagship mobile SoC," in Proc. IEEE Int. Solid-State Circuits Conf.-(ISSCC), San Francisco, CA, USA, Feb. 17-21, 2019, doi: 10.1109/ISSCC.2019.8662476.
- www.arm.com/products/silicon-ip-cpu/ethos/ethos-n77, n57, n37
- www.ceva-dsp.com/product/ceva-neupro/
- www.gyrfalcontech.ai/solutions/2801s, 2801s
- www.ces.tech/Innovation-Awards/Honorees/2020/Honorees/H/Hailo-8.aspx
- H. Orr Danon, "Introducing Hailo-8: The Most Efficient Deep Learning Processor for Edge Devices," 2019 Embedded Vision Summit, May 2019.
- E. Lindholm et al., "NVIDIA Tesla: A Unified Graphics and Computing Architecture," IEEE Micro, vol. 28, no. 2, 2008, pp. 39-55. https://doi.org/10.1109/MM.2008.31
- NVIDIA, "Nvidia Tesla V100 GPU Architecture," WP-08608-001_v1.1, 2017, https://images.nvidia.com/content/voltaarchitecture/pdf/volta-architecture-whitepaper.pdf.
- D. Patterson, "Domain Specific Architectures for Deep Neural Networks: Three Generations of Tensor Processing Units (TPUs)," Allen School Distinguished Lecture: David Patterson (UC Berkeley/Google)
- N. P. Jouppi et al., "In-Datacenter Performance Analysis of a Tensor Processing Unit," in Proc. Annu. Int. Symp. Comput. Architect., Toronto, Canada, June 2017 doi: 10.1145/3079856.3080246.
- caffe.berkeleyvision.org
- Y. Kwon et al., "Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture," in Proc. Annu. Int. Conf. Artif. Intell. Circuits Syst., Hsinchu, Taiwan, Mar. 2019, doi: 10.1109/AICAS.2019.8771603 .