• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.801-805
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• 2009

The importance of high-speed networking is ever increasing to better support multimedia application such as video conferencing. It is crucial to synchronize the network so that the delay between computers on the network is minimized. In high-speed LAN, for example, most computers use clocks with almost same frequency to minimize the delay for data transmission. However, because of the deviation of transmitter's and receiver's clock frequency and phase difference there can be a metastability problem. Elasticity buffer is to provide a solution for this situation and this paper presents an implementation is a high-speed elasticity buffer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.130-136
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• 1989

Electrical transport and thermally induced metastability in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) using boron-doped amorphous silicon as an active layer have been studied. The device characteristics n-channel and p-channel operations. The thermal quenching experiments on amorphous silicon-silicon nitride ambipolar TFT give clear evidence for the co-existence of two distinct metastable changes. The densities of metastable active dopants and dangling bonds increase with the quenching temperature. On the other hand, the interface state density appears to decrease with increasing quenching temperature.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1038-1041
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• 2005

In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

• Proceedings of the Korean Biophysical Society Conference
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• 2001.06a
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• pp.62-62
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• 2001

Serpins inhibit target proteases by forming tight acyl complex Via incorporation of the reactive center loop into ${\beta}$-sheet A. Metastability of the serpins control the translocation of the protease from the initial binding site to the opposite pole of the serpin. Recently the crystal structure of a serpin-protease complex revealed that the active site of the protease is distorted.(omitted)

• Journal of IKEEE
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• v.24 no.2
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• pp.543-549
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• 2020

As the importance of security increases in various fields, research on a random number generator (RNG) used for generating an encryption key, has been actively conducted. A high-quality RNG is essential to generate a high-performance encryption key, but the initial pseudo-random number generator (PRNG) has the possibility of predicting the encryption key from the outside even though a large amount of hardware resources are required to generate a sufficiently high-performance random number. Therefore, the demand of high-quality true random number generator (TRNG) generating random number through various noises is increasing. This paper examines and compares the representative TRNG methods based on metastable-based and ring-oscillator-based TRNGs. We compare the methods how the random sources are generated in each TRNG and evaluate its performances using NIST SP 800-22 tests.

• Proceedings of the Korean Biophysical Society Conference
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• 1998.06a
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• pp.23-23
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• 1998

To understand structural and functional basis of loaded energy in the metastable native structure of inhibitory serpins (serine protease inhibitors), we characterized mutations that decreased the loaded energy of ${\alpha}$$_1$-antitrypsin and simultaneously influenced its inhibitory activity. Various folding defects such as side-chain locking, buried polar groups in unfavorable hydrophobic environment, and cavities were found as the structural basis of the metastability of ${\alpha}$$_1$-antitrypsin in a region presumably directly involved in the formation of complex between the inhibitor and a target protease.(omitted)

• Proceedings of the Korean Biophysical Society Conference
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• 1996.07a
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• pp.4-4
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• 1996

$\alpha$$_1$-arantitrypsin, a member of the serpin (serine protease inhibitor) family, undergoes a large structural rearrangement upon the cleavage and insertion of the reactive site loop. This conformational change is driven by the metastability of the native serpin structures and has an important role in the regulation of the inhibitory-serpin function. (omitted)

• Proceedings of the Korean Biophysical Society Conference
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• 1999.06a
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• pp.42-42
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• 1999

Metastability in the native form of proteins has been recognized as a mechanism of biological regulation. The strained native structure of serpins (serine proteinase inhibitors) is a typical example. The native strain of serpins is considered to be crucial to their physiological functions, such as plasma proteinase inhibition, hormone delivery, Alzheimer filament assembly, and extracellular matrix remodeling.(omitted)

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.59-63
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• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.