• Journal of Ceramic Processing Research
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• v.13 no.spc1
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• pp.128-131
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• 2012

The selective area growth light emitting diode on GaN substrate was grown using mixed-source HVPE method with multi-sliding boat system. The GaN substrate was grown using mixed-source HVPE system. Te-doped AlGaN/AlGaN/Mg-doped AlGaN/Mg-doped GaN multi-layers were grown on the GaN substrate. The appearance of epi-layers and the thickness of the DH was evaluated by SEM measurement. The DH metallization was performed by e-beam evaporator. n-type metal and p-type metal were evaporated Ti/Al and Ni/Au, respectively. At the I-V measurement, the turn-on voltage is 3 V and the differential resistance is 13 Ω. It was found that the SAG-LED grown on GaN substrate using mixed-source HVPE method with multi-sliding boat system could be applied for developing high quality LEDs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.5
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• pp.507-511
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• 2024

Various process modifications have been used to minimize SiO₂ gate oxide aging in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, post-metallization annealing (PMA) with a deuterium ambient can effectively eliminate both bulk traps and interface traps in the gate oxide. However, even with the use of PMA, it remains difficult to prevent high levels of radiation-induced gate oxide damage such as total ionizing dose (TID) during long-term missions. In this context, additional low-temperature heat treatment (LTHT) is proposed to recover from radiation-induced damage. Positive traps in the damaged gate oxide can be neutralized using LTHT, thereby prolonging device reliability in harsh radioactive environments.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.12
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• pp.1015-1020
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• 2012

Resistance of the front electrode is the highest proportion of the ingredients of the series resistance in crystalline silicon solar cell. While resistance of the front electrode is decreased with larger area, it induces the optical loss, causing the conversion efficiency drop. Therefore the front electrode with high aspect ratio increasing its height and decreasing is necessary for high-efficiency solar cell in considering shadowing loss and resistance of front electrode. In this paper, we used the screen printing method to form high aspect ratio electrode by multiple printing. Screen printing is the straightforward technology to establish the electrodes in silicon solar cell fabrication. The several printed front electrodes with Ag paste on silicon wafer showed the significantly increased height and slightly widen finger. As a result, the resistance of the front electrode was decreased with multiple printing even if it slightly increased the shadowing loss. We showed the improved electrical characteristics for c-Si solar cell with repeatedly printed front electrode by 0.5%. It lays a foundation for high efficiency solar cell with high aspect ratio electrode using screen printing.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.39-44
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• 2015

We investigated the effect of CNT-Ag composite pad on the contact resistance of flip-chip joints, which were formed by flip-chip bonding of Cu/Au chip bumps to Cu substrate metallization using anisotropic conductive adhesive. Lower contact resistances were obtained for the flip-chip joints which contained the CNT-Ag composite pad than the joints without the CNT-Ag composite pad. While the flip-chip joints with the CNT-Ag composite pad exhibited average contact resistances of $164m{\Omega}$, $141m{\Omega}$, and $132m{\Omega}$ at bonding pressures of 25 MPa, 50 MPa, and 100 MPa, the flip-chip joints without the CNT-Ag composite pad had an average contact resistance of $200m{\Omega}$, $150m{\Omega}$, and $140m{\Omega}$ at each bonding pressure.

• Korean Journal of Materials Research
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• v.21 no.3
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• pp.174-179
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• 2011

Ultra-thin aluminum (Al) and tin (Sn) films were grown by dc magnetron sputtering on a glass substrate. The electrical resistance R of films was measured in-situ method during the film growth. Also transmission electron microscopy (TEM) study was carried out to observe the microstructure of the films. In the ultra-thin film study, an exact determination of a coalescence thickness and a continuous film thickness is very important. Therefore, we tried to measure the minimum thickness for continuous film (dmin) by means of a graphical method using a number of different y-values as a function of film thickness. The raw date obtained in this study provides a graph of in-situ resistance of metal film as a function of film thickness. For the Al film, there occurs a maximum value in a graph of in-situ electrical resistance versus film thickness. Using the results in this study, we could define clearly the minimum thickness for continuous film where the position of minimum values in the graph when we put the value of Rd3 to y-axis and the film thickness to x-axis. The measured values for the minimum thickness for continuous film are 21 nm and 16 nm for sputtered Al and Sn films, respectively. The new method for defining the minimum thickness for continuous film in this study can be utilized in a basic data when we design an ultra-thin film for the metallization application in nano-scale devices.

• Korean Journal of Materials Research
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• v.21 no.2
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• pp.95-99
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• 2011

The microstructure and Cu diffusion barrier property of Ta-Si-N films for various Si and N compositions were studied. Ta-Si-N films of a wide range of compositions (Si: 0~30 at.%, N: 0~55 at.%) were deposited by DC magnetron reactive sputtering of Ta and Si targets. Deposition rates of Ta and Si films as a function of DC target current density for various $N_2/(Ar+N_2)$ flow rate ratios were investigated. The composition of Ta-Si-N films was examined by wavelength dispersive spectroscopy (WDS). The variation of the microstructure of Ta-Si-N films with Si and N composition was examined by X-ray diffraction (XRD). The degree of crystallinity of Ta-Si-N films decreased with increasing Si and N composition. The Cu diffusion barrier property of Ta-Si-N films with more than sixty compositions was investigated. The Cu(100 nm)/Ta-Si-N(30 nm)/Si structure was used to investigate the Cu diffusion barrier property of Ta-Si-N films. The microstructure of all Cu/Ta-Si-N/Si structures after heat treatment for 1 hour at various temperatures was examined by XRD. A contour map that shows the diffusion barrier failure temperature for Cu as a function of Si and N composition was completed. At Si compositions ranging from 0 to 15 at.%, the Cu diffusion barrier property was best when the composition ratio of Ta + Si and N was almost identical.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.213-224
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• 2010

An optically controlled silicon MESFET (OPFET) was fabricated by diffusion process to enhance the quantum efficiency, which is the most important optoelectronic device performance usually affected by ion implantation process due to large number of process induced defects. The desired impurity distribution profile and the junction depth were obtained solely with diffusion, and etching processes monitored by atomic force microscope, spreading resistance profiling and C-V measurements. With this approach fabrication induced defects are reduced, leading to significantly improved performance. The fabricated OPFET devices showed proper I-V characteristics with desired pinch-off voltage and threshold voltage for normally-on devices. The peak photoresponsivity was obtained at 620 nm wavelength and the extracted external quantum efficiency from the photoresponse plot was found to be approximately 87.9%. This result is evidence of enhancement of device quantum efficiency fabricated by the diffusion process. It also supports the fact that the diffusion process is an extremely suitable process for fabrication of high performance optoelectronic devices. The maximum gain of OPFET at optical modulated signal was obtained at the frequency of 1 MHz with rise time and fall time approximately of 480 nS. The extracted transconductance shows the possible potential of device speed performance improvements for shorter gate length. The results support the use of a diffusion process for fabrication of high performance optoelectronic devices.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.280-288
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• 2016

Microelectronic product consumers may already be expecting another paradigm shift with smarter phones over smart phones, but the current status of microelectronic manufacturing engineering education (MMEE) in universities hardly makes up the pace for such a fast moving technology paradigm shift. The purpose of MMEE is to educate four-year university graduates to work in the microelectronics industry with up-to-date knowledge and self-motivation. In this paper, we present a comprehensive curriculum for a four-year university degree program in the area of microelectronics manufacturing. Three hands-on experienced-based courses are proposed, along with a methodology for undergraduate students to acquire hands-on experience, towards integrated circuits (ICs) design, fabrication and packaging, are presented in consideration of manufacturing engineering education. Semiconductor device and circuit design course for junior level is designed to cover how designed circuits progress to micro-fabrication by practicing full customization of the layout of digital circuits. Hands-on experienced-based semiconductor fabrication courses are composed to enhance students’ motivation to participate in self-motivated semiconductor fab activities by performing a series of collaborations. Finally, the Microelectronics Packaging course provides greater possibilities of mastered skillsets in the area of microelectronics manufacturing with the fabrication of printed circuit boards (PCBs) and board level assembly for microprocessor applications. The evaluation of the presented comprehensive curriculum was performed with a students’ survey. All the students responded with “Strongly Agree” or “Agree” for the manufacturing related courses. Through the development and application of the presented curriculum for the past six years, we are convinced that students’ confidence in obtaining their desired jobs or choosing higher degrees in the area of microelectronics manufacturing was increased. We confirmed that the hypothesis on the inclusion of handson experience-based courses for MMEE is beneficial to enhancing the motivation for learning.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.215-216
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• 2013

The silicide is a compound of Si with an electropositive component. Silicides are commonly used in silicon-based microelectronics to reduce resistivity of gate and local interconnect metallization. The popular silicide candidates, CoSi2 and TiSi2, have some limitations. TiSi2 showed line width dependent sheet resistance and has difficulty in transformation of the C49 phase to the low resistive C54. CoSi2 consumes more Si than TiSi2. Nickel silicide is a promising material to substitute for those silicide materials providing several advantages; low resistivity, lower Si consumption and lower formation temperature. Nickel silicide (NiSi) nanowire (NW) has features of a geometrically tiny size in terms of diameter and significantly long directional length, with an excellent electrical conductivity. According to these advantages, NiSi NWs have been applied to various nanoscale applications, such as interconnects [1,2], field emitters [3], and functional microscopy tips [4]. Beside its tiny geometric feature, NW can provide a large surface area at a fixed volume. This makes the material viable for photovoltaic architecture, allowing it to be used to enhance the light-active region [5]. Additionally, a recent report has suggested that an effective antireflection coating-layer can be made with by NiSi NW arrays [6]. A unique growth mechanism of nickel silicide (NiSi) nanowires (NWs) was thermodynamically investigated. The reaction between Ni and Si primarily determines NiSi phases according to the deposition condition. Optimum growth conditions were found at $375^{\circ}C$ leading long and high-density NiSi NWs. The ignition of NiSi NWs is determined by the grain size due to the nucleation limited silicide reaction. A successive Ni diffusion through a silicide layer was traced from a NW grown sample. Otherwise Ni-rich or Si-rich phase induces a film type growth. This work demonstrates specific existence of NiSi NW growth [7].

• Journal of Intelligence and Information Systems
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• v.15 no.4
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• pp.213-224
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• 2009

This paper describes a real-time scheduling system re-construction project for automated manufacturing at a 300mm wafer fab of Korean semiconductor manufacturing company. During executing this project, for each main operation such as clean, diffusion, deposition, photolithography, and metallization, each adopted scheduling algorithm was developed, and then those were implemented in a real-time scheduling system. In this paper, we focus on the scheduling algorithms and real-time scheduling system for clean and diffusion operations, that is, a serial-process block with the constraint of limited queue time and batch processors. After this project was completed, the automated manufacturing utilizations of clean and diffusion operations became around 91% and 83% respectively, which were about 50% and 10% at the beginning of this project. The automated manufacturing system reduces direct operating costs, increased throughput on the equipments, and suggests continuous and uninterrupted processings.