• The KIPS Transactions:PartC
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• v.15C no.3
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• pp.149-156
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• 2008

JPEG2000 is the upcoming image coding standard that provides better compression rate and image quality compared with JPEG. Lazy-mode steganography guarantees the safe communication under the two information loss stages in JPEG2000. However, it causes the severe changes of the code-block noise variance sequence after embedding and that is detectable under the steganalysis using the Hilbert-Huang transform (HHT) based sequential analysis. In this paper, a JPEG2000 lazy-mode steganography method is presented. The code blocks which produce the sudden variation of the noise variance after embedding are estimated by calculating low precision code-block variance (LPV) and low precision code-block noise variance (LPNV). By avoiding those code-blocks from embedding, our algorithm preserves the sequence and makes stego images secure under the HHT-based steganalytic detection. In addition, it prevents a severe degradation of image quality by using JPEG2000 quality layer information. On various 2048 images, experiments are performed to show the effective reduction of the noise variation after message embedding and the stable performance against HHT-based steganalysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1444-1455
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• 1999

In the standard location strategy such as IS-41 and GSM, Home Location Register(HLR) and Visitor Location Register(VLR) databases are used to manage the location of mobile terminals. The primary goal that location management schemes investigate is to reduce the cost of database access and the traffic for signaling network. When mobile terminals move frequently, one of problems in the standard location management scheme is that HLR database is highly updated and the traffic in signaling network can be occurred significantly due to high message transfer rate between HRL and VLR. As a solution to these problems, this paper proposes the location management scheme using VLR Gateway(VG) to reduce the both traffics of HLR update and signaling network which are resulted from location registration requirements of mobile terminals whenever they cross their registration area boundary. VG is a kind of database that is placed between HLR and VLR. It integrates one or more registration area defined in a system into one group and plays a role on behalf of HLR in a integrated registration scope so that the call delivery and the movement of mobile terminals are possible without HLR access in the scope. In order to evaluate performance of IS-41 and proposed scheme, we simulate two schemes based on wide range of call to mobility ratio. Its experiment result shows that in the proposed scheme total database cost increased slightly whereas HLR and signaling traffic decreased remarkably.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.1
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• pp.39-47
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• 2005

The range of hardware implementation increases in communication systems as high-speed processing is required for high data rate. In the broadband wireless access (BWA) system based on IEEE standard 802.16 the functions of higher part in the MAC layer to Provide data needed for generating MAC PDU are implemented in software, and the tasks from formatting MAC PDUs by using those data to transmitting the messages in a modem are implemented in hardware. In this paper, the interface hardware for efficient message exchange between MAC and PHY layers in the BWA system is designed. The hardware performs the following functions including those of the transmission convergence(TC) sublayer; (1) formatting TC PDU(Protocol data unit) from/to MAC PDU, (2) Reed-solomon(RS) encoding/decoding, and (3) resolving DL MAP and UL MAP, so that it controls transmission slot and uplink and downlink traffic according to the modulation scheme of burst profile. Also, it provides various control signal for PHY modem. In addition, the truncated binary exponential backoff (TBEB) algorithm is implemented in a subscriber station to avoid collision on contention-based transmission of messages. The VLSI architecture performing all these functions is implemented and verified in VHDL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.128-138
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• 2010

In this paper, we propose a new bit assignment scheme for Wyner-Ziv video coding. Distributed video coding (DVC) is a new video coding paradigm which enables greatly low complexity encoding because it does not have any motion prediction module at encoder. Therefore, it is very well suited for many applications such as video communication, video surveillance, extremely low power consumption video coding, and other portable applications. Theoretically, the Wyner-Ziv video coding is proved to achieve the same rate-distortion (RD) performance comparable to that of the joint video coding. However, its RD performance has much gap compared to MC-DCT-based video coding such as H.264/AVC. Moreover, Transform Domain Wyner-Ziv (TDWZ) video coding which is a kind of DVC with transform module has difficulty of exact bit assignment because the entire image is treated as a same message. In this paper, we propose a feasible bit assignment algorithm using adaptive quantization matrix selection for the TDWZ video coding. The proposed method can calculate suitable bit amount for each region using the local characteristics of image. Simulation results show that the proposed method can enhance coding performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Science of Emotion and Sensibility
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• v.9 no.2
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• pp.93-100
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• 2006

This paper aims at the development and clinical evaluation of the wireless gyro-mouse system. The wireless gyro-mouse system is a computer interface with gyro-sensor and wireless communication, for the patients with upper-extremity disabled from the traffic accident or stroke to use the computer software i.e. internet browser. In the development, we focused on, firstly, to make the system wireless for the patients to manipulate the mouse easily even on the bed or wheelchair, secondly, to insert the gyro-sensor into a headband for easy don-and-doff and aesthetic appearance, thirdly, to devise a click switch in case of $C5{\sim}C6$ patients and a head nodding detection in case of C4 patients for sending click message to computer operating system. We performed evaluation experiment for patients with upper-extremities disabled from spinal cord injury. The results show that the displacement error of the cursor position against the target position during linear (vertical/horizontal) movement manipulation decreased with trial number. The click rate per minute also increased with trial number. This indicates the developed wireless gyro-mouse system would be more useful to the patients with repetitive use.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.4
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• pp.36-43
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• 2011

The forward collision of vehicles in high speed can cause a chain collisions and high fatality rate. Most of the forward collisions are caused by insufficient braking distance due to detection time of driver and safe distance. Also, accumulated detection time of driver is cause of chain collisions after the forward collision. The FVCWS prevents the forward collision by maintaining the safety distance inter-vehicle and reducing detection time of driver. However the FVCWS can cause chain collisions because the system that interacts only forward vehicle has accumulated detection time of driver. In this paper, we analyze forward and chain collisions of normal vehicles and FVCWS vehicles on static traveling scenario. And then, we analyze and compare V2V based FVCWS with them after explaining the system. The V2V FVCWS reduces detection time of driver alike FVCWS as well as remove accumulated detection time of driver by broadcasting emergence message to backward vehicles at the same time. Therefore, the system decrease possibility of forward and chain collisions. All backward normal vehicles and 3~4 backward FVCWS vehicles have possibility of forward and chain collisions in result of analysis. However V2V FVCWS vehicles almost do not chain collisions in the result.