• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.5
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• pp.74-82
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• 2011

SSD has a limitation of number of erase/write cycles and does not allow in-place update unlike the hard disk because SSD is composed of an array of NAND flash memory. Thus, FTL is used to effectively manage SSD of having different characteristics from traditional disk. FTL has page, block, log-block mapping method. Among then, when log-block mapping method such as BAST and FAST is used, the performance of SSD is degraded because frequent merge operations cause lots of pages to be copied and deleted. This paper proposes a data allocation and replacement method based on access frequency by allocating PRAM as checking area of access frequency, log blocks, storing region of hot data in SSD. The proposed method can enhance the performance and lifetime of SSD by storing cold data to flash memory and storing log blocks and frequently accessed data to PRAM and then reducing merge and erase operations. Besides, a data replacement method is used to increase utilization of PRAM which has limitation of capacity. The experimental results show that the ratio of erase operations of the proposed method is 46%, 38% smaller than those of BAST and FAST and the write performance of the proposed method is 34%, 19% higher than those of BAST and FAST, and the read performance of the proposed method is 5%, 3% higher than those of BAST and FAST, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.

• Journal of KIISE:Databases
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• v.29 no.4
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• pp.321-333
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• 2002

As web-based services are becoming more and more popular, concurrent updates of spatial data should be possible in the web-based environments in order to use the various services. Web-based GIS applications are characterized by large quantity of data providing and these data should be continuously updated according to various user's requirements. Faced with such an enormous data providing system, it is inefficient for a server to do all of the works of updating spatial data requested by clients. Besides, the HTTP protocol used in the web environment is established under the assumption of 'Connectionless'and 'Stateless'. Lots of problems may occur if the scheme of transaction processing based on the LAN environment is directly applied to the web environment. Especially for long transactions of updating spatial data, it is very difficult to control the concurrency among clients and to keep the consistency of the server data. This paper proposes a solution of keeping consistency during updating directly spatial data in the client-side by resolving the Dormancy Region Lock problem caused by the 'Connectionless'and 'Stateless'feature of the HTTP protocol. The RX(Region-eXclusive) lock and the periodically sending of ALIVE_CLIENTi messages can solve this problem. The protocol designed here is verified as effective enough through implementing in the main memory spatial database system, called CyberMap.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.3
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• pp.191-198
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• 2009

The FAT (File Allocation Table) compatible file system has been widely used in mobile devices and memory cards because of its data exchangeability among numerous platforms recognizing the FAT file system. By the way. modern embedded systems have tough demands for instant power failure recovery and superior performance for multimedia applications. The key issue is how to achieve the goals of superior write performance and instant booting capability while controlling compatibility issues. To achieve the goals while controlling compatibility issues. we devised a temporary meta-data journaling scheme for a FAT compatible file system. Benchmark results of the scheme implemented in a FAT compatible file system shows that it really improves write performance of the FAT file system by converting small random write for meta-data update to a large sequential write in journaling area. Also, it provides natural way to implement the instant booting capability. Nevertheless, the file system compatibility is temporarily compromised by the scheme because it stores updated meta-data in the temporary journaling area rather than to their original locations. However, the compatibility can be fully recovered at any time by journal-flushing that copies meta-data in journaling area to their original locations. Generally, the journal-flushing is done before un-mounting a memory card so that it can be used in other mobile devices which recognized FAT file system but not the temporary meta-data journaling scheme.

• Journal of the Korea Society for Simulation
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• v.32 no.3
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• pp.43-53
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• 2023

In this detailed and comprehensive study, our primary focus has been placed on accurately gauging the number of visitors and their real-time locations in commercial spaces. Particularly, in a real cafe, using security cameras, we have developed a system that can offer live updates on available seating and predict future congestion levels. By employing YOLO, a real-time object detection and tracking algorithm, the number of visitors and their respective locations in real-time are also monitored. This information is then used to update a cafe's indoor map, thereby enabling users to easily identify available seating. Moreover, we developed a model that predicts the congestion of a cafe in real time. The sophisticated model, designed to learn visitor count and movement patterns over diverse time intervals, is based on Long Short Term Memory (LSTM) to address the vanishing gradient problem and Sequence-to-Sequence (Seq2Seq) for processing data with temporal relationships. This innovative system has the potential to significantly improve cafe management efficiency and customer satisfaction by delivering reliable predictions of cafe congestion to all users. Our groundbreaking research not only demonstrates the effectiveness and utility of indoor location tracking technology implemented through security cameras but also proposes potential applications in other commercial spaces.

• Journal of Korea Multimedia Society
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• v.10 no.8
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• pp.1029-1038
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• 2007

A smart card based on the existing Java card platform executes and installs an application only when the power is supplied for a minute. And preparing for unexpected power outrage, the execution state of an application and all the data that are modified during execution are saved in the heap. This kind of frequent data update of an EEPROM data is a main cause of reducing the life-cycle of a smart card. This is because the smart card has been developed not considering the current situation that the power is always supplied, and by this time it has continuously kept its old architecture. This paper explains the high performance Java card system free power restriction. The system improves not only application saving mechanism, but memory architecture. In special, we deploy RAM for running an applet, as well as EEPROM for downloading an application. Through proposed mechanism, we can find out performance evaluation that the creation speed of an applet and the execution speed of a method increase up to 58% and 33% respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.103-113
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• 2001

This paper described a design and implementation of a single-chip encoder/decoder using the LZSS algorithm and entropy coding in 0.6${\mu}{\textrm}{m}$ CMOS technology. Dictionary storage for the dictionary search processor(DISP) used a 2K$\times$8bit on-chip memory with 50MHz clock speed. It performs compression on byte-oriented input data at a data rate of one byte per clock cycle except when one out of every 33 cycles is used to update the string window of dictionary. In result, the average compression ratio is 46% by applied entropy coding of the LZSS codeword output. This is to improved on the compression performance of 7% much more then LZSS.

• Journal of Korean Society for Geospatial Information Science
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• v.20 no.2
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• pp.81-91
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• 2012

As the recent development of the ubiquitous computing environment, u-GIS is being highlighted as the core technology of the ubiquitous computing environment, and thereby, studies on spatio-temporal data are being actively conducted. In this u-GIS environment, it is still difficult for existing mobile devices to efficiently manage the massive spatio-temporal data of u-GIS that are increasing day by day. Therefore, this paper develops a spatio-temporal query processing system for mobile devices in order to solve the problem. The system provides various spatio-temporal operators to insert/delete/update/search spatio-temporal data and supports a query optimization function that uses a spatio-temporal index for the flash memory and a spatio-temporal histogram for guaranteeing query execution speed. Lastly, by applying the spatio-temporal query processing system developed in this paper to the virtual scenario, this paper has proved that the system can be utilized in various application fields necessary to process spatio-temporal data in the mobile environment.

• Journal of the Korea Society of Computer and Information
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• v.16 no.4
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• pp.169-177
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• 2011

As demand for efficiency in handling dynamic XML data grows, new dynamic XML labeling schemes have been researched. The key idea of the dynamic XML labeling scheme is to find ancestor-descendent-sibling relationships and to minimize memory space to store total label, response time and range of relabeling incurred by update operations. The prime number labeling scheme is a representative scheme which supports dynamic XML documents. It determines the ancestor-descendant relationships between two elements by a simple divisibility test of labels. When a new element is inserted into the XML data using this scheme, it does not change the label values of existing nodes. However, since each prime number must be used exclusively, labels can become significantly large. Therefore, in this paper, we introduce a novel technique to effectively reduce the problem of label overflow. The suggested idea is based on tree decomposition. When label overflow occurs, the full tree is divided into several sub-trees, and nodes in each sub-tree are separately labeled. Through experiments, we show the effectiveness of our scheme.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.