• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.205-208
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• 2002

An existing ATM switch fabric uses VPI(Virtual Path Identifier) and VCI(Virtual Channel Identifier) information to route ATM cell. But AAL type 2 switch which efficiently processes delay-sensitive, low bit-rate data such as a voice routes the ATM cell by using CID(Channel Identification) field in addition to VPI and VCI. In this paper, we research the AAL type 2 switch that performs the process of CPS packet. The Receive unit extracts the CPS packet from the inputted ATM cell. The designed receive unit consists of input FIFO, r)( status table, CAM(Content Addressable Memory), new CID table and partial packet memory. Also the designed receive unit supports the PCI interface with host processor. The receive unit is implemented in Xilinx FPGA and operates at 72MHz.

• Journal of the Korea Society of Computer and Information
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• v.17 no.7
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• pp.1-11
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• 2012

As process technology scales down, the number of cores integrated into a processor increases dramatically, leading to significant performance improvement. Especially, the GPU(Graphics Processing Unit) containing many cores can provide high computational performance by maximizing the parallelism. In the GPU architecture, the access latency to the main memory becomes one of the major reasons restricting the performance improvement. In this work, we analyze the performance improvement of the 3D GPU architecture compared to the 2D GPU architecture quantitatively and investigate the potential problems of the 3D GPU architecture. In general, memory instructions account for 30% of total instructions, and global/local memory instructions constitutes 60% of total memory instructions. Therefore, the performance of the 3D GPU is expected to be improved significantly compared to the 2D GPU by reducing the delay of memory instructions. However, according to our experimental results, the 3D architecture improves the GPU performance only by 2% compared to the 2D architecture due to the memory bottleneck, since the performance reduction due to memory bottleneck in the 3D GPU architecture increases by 245% compared to the 2D architecture. This paper provides the guideline for suitable memory design by analyzing the efficiency of the memory architecture in 3D GPU architecture.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.339-349
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• 2011

IBDI (Internal Bit Depth Increase) is able to significantly improve the coding efficiency of high definition video compression by increasing the bit depth (or precision) of internal arithmetic operation. However the scheme also increases required internal memory for storing decoded reference frames and this can be significant for higher definition of video contents. So, the reference frame memory compression method is proposed to reduce such internal memory requirement. The reference memory compression is performed on 4x4 block called the processing unit to compress the decoded image using the correlation of nearby pixel values. This method has successively reduced the reference frame memory while preserving the coding efficiency of IBDI. However, additional information of each processing unit has to be stored also in internal memory, the amount of additional information could be a limitation of the effectiveness of memory compression scheme. To relax this limitation of previous memory compression scheme, we propose a selective merging-based reference frame memory compression algorithm, dramatically reducing the amount of additional information. Simulation results show that the proposed algorithm provides much smaller overhead than that of the previous algorithm while keeping the coding efficiency of IBDI.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.222-227
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• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.211-218
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• 2001

In this paper, we propose the structure of utilizing the memory map, which is using not conventional DRAM but SDRAM, for the hardware implementation of frame memory interface module to the video encoder. As reducing the size of memory map and interface buffer within the same bus, the hardware complexity is improved and the hardware size is minimized as simplifying the interface logic. The conventional system is wasted access time, because of accessing randomly stored data in order to store and output the memories in macro-block unit. therefore the method, which is proposed in this paper, can be effectively reducing the access time of memory, because of the data is stored and processed by line unit.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.4
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• pp.389-394
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• 2010

This paper describes the conceptual design of mass memory unit for high speed data processing and mass memory management in the STSAT-3 compared to that of STSAT-2. The FPGA directly controls the data receiving from two payloads with the maximum 100Mbps speed and 32Gb mass memory management to satisfy these requirements. We used SRAM-based FPGA from XILINX having fast operating speed and large logic cells. Therefore, the Triple Modular Redundancy(TMR) and configuration memory scrubbing techniques will also be used to protect FPGA from Single Event Upset(SEU) in space.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.11
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• pp.115-120
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• 2005

This paper describes the design and implementation of engineering model(EM) of Mass Memory Unit(MMU) for Science and Technology Satellite 2(STSAT-2) and the results of integration test. The use of Field-Programmable Gate Array(FPGA) instead of using private electric parts makes a miniaturization and lightweight of MMU possible. 2Gbits Synchronous Dynamic Random Access Memory(SDRAM) module for mass memory is used to store payload and satellite status data. Moreover, file system is applied to manage them easily in the ground station. RS(207,187) code improves the tolerance with respect to Single Event Upset(SEU) induced in SDRAM. The simulator is manufactured to verify receiving performance of payload data.