• Title/Summary/Keyword: memory switching

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Mutually-Actuated-Nano-Electromechanical (MA-NEM) Memory Switches for Scalability Improvement

  • Lee, Ho Moon;Choi, Woo Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.2
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    • pp.199-203
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    • 2017
  • Mutually-actuated-nano-electromechanical (MA-NEM) memory switches are proposed for scalability improvement. While conventional NEM memory switches have fixed electrode lines, the proposed MA-NEM memory switches have mutually-actuated cantilever-like electrode lines. Thus, MA-NEM memory switches show smaller deformations of beams in switching. This unique feature of MA-NEM memory switches allows aggressive reduction of the beam length while maintaining nonvolatile property. Also, the scalability of MA-NEM memory switches is confirmed by using finite-element (FE) simulations. MA-NEM memory switches can be promising solutions for reconfigurable logic (RL) circuits.

Electrical Characteristics of Resistive-Switching-Memory Based on Indium-Zinc-Oxide Thin-Film by Solution Processing (용액 공정을 이용한 Indium-Zinc-Oxide 박막 기반 저항 스위칭 메모리의 전기적 특성)

  • Kim, Han-Sang;Kim, Sung-Jin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.30 no.8
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    • pp.484-490
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    • 2017
  • We investigated the rewritable operation of a non-volatile memory device composed of Al (top)/$TiO_2$/indium-zinc-oxide (IZO)/Al (bottom). The oxygen-deficient IZO layer of the device was spin-coated with 0.1 M indium nitrate hydrate and 0.1 M zinc acetate dehydrate as precursor solutions, and the $TiO_2$ layer was fabricated by atomic layer deposition. The oxygen vacancies IZO layer of an active component annealed at $400^{\circ}C$ using thermal annealing and it was proven to be in oxygen vacancies and oxygen binding environments with OH species and heavy metal ions investigated by X-ray photoelectron spectroscopy. The device, which operates at low voltages (less than 3.5 V), exhibits non-volatile memory behavior consistent with resistive-switching properties and an ON/OFF ratio of approximately $3.6{\times}10^3$ at 2.5 V.

Microwave Annealing in Ag/HfO2/Pt Structured ReRAM Device

  • Kim, Jang-Han;Kim, Hong-Ki;Jang, Ki-Hyun;Bae, Tae-Eon;Cho, Won-Ju;Chung, Hong-Bay
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.373-373
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    • 2014
  • Resistive-change random access memory (ReRAM) device is one of the promising candidates owing to its simple structure, high scalability potential and low power operation. Many resistive switching devices using transition metal oxides materials such as NiO, Al2O3, ZnO, HfO2, $TiO_2$, have attracting increased attention in recent years as the next-generation nonvolatile memory. Among various transition metal oxides materials, HfO2 has been adopted as the gate dielectric in advanced Si devices. For this reason, it is advantageous to develop an HfO2-based ReRAM devices to leverage its compatibility with Si. However, the annealing temperature of these high-k thin films for a suitable resistive memory switching is high, so there are several reports for low temperature process including microwave irradiation. In this paper, we demonstrate the bipolar resistive switching characteristics in the microwave irradiation annealing processed Ag/HfO2/Pt ReRAM device. Compared to the as-deposited Ag/HfO2/Pt device, highly improved uniformity of resistance values and operating voltage were obtained from the micro wave annealing processed HfO2 ReRAM device. In addition, a stable DC endurance (>100 cycles) and a high data retention (>104 sec) were achieved.

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Linux-based Memory Efficient Partition Scheduler using Partition Bitmap (파티션 비트맵을 이용한 메모리 효율적인 리눅스 파티션 스케줄러)

  • Kwon, Cheolsoon;Joe, Hyunwoo;Kim, Duksoo;Kim, Hyungshin
    • KIISE Transactions on Computing Practices
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    • v.20 no.9
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    • pp.519-524
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    • 2014
  • The operating systems in the system architecture, which is integrated several applications and modular electronic devices in the same computing device, demand partitioning technology for safety. Thus, operation system requires partition scheduler for partition scheduling. When we design partition scheduler in embedded system, which has small memory and low performance, such as space system, we must consider not only performance but also memory. In this paper, we introduces a linux-based memory efficient partition scheduler using partition bitmap. This partition scheduler demands small memory space and produce low partition switching overhead. The prototype was executed on a LEON4 processor, which is the Next Generation Multicore Processor (NGMP) in the space sector. In evaluation, this prototype shows accuracy, additional memory space and low partition switching overhead.

Deep reinforcement learning for base station switching scheme with federated LSTM-based traffic predictions

  • Hyebin Park;Seung Hyun Yoon
    • ETRI Journal
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    • v.46 no.3
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    • pp.379-391
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    • 2024
  • To meet increasing traffic requirements in mobile networks, small base stations (SBSs) are densely deployed, overlapping existing network architecture and increasing system capacity. However, densely deployed SBSs increase energy consumption and interference. Although these problems already exist because of densely deployed SBSs, even more SBSs are needed to meet increasing traffic demands. Hence, base station (BS) switching operations have been used to minimize energy consumption while guaranteeing quality-of-service (QoS) for users. In this study, to optimize energy efficiency, we propose the use of deep reinforcement learning (DRL) to create a BS switching operation strategy with a traffic prediction model. First, a federated long short-term memory (LSTM) model is introduced to predict user traffic demands from user trajectory information. Next, the DRL-based BS switching operation scheme determines the switching operations for the SBSs using the predicted traffic demand. Experimental results confirm that the proposed scheme outperforms existing approaches in terms of energy efficiency, signal-to-interference noise ratio, handover metrics, and prediction performance.

MRAM Technology for High Density Memory Application

  • Kim, Chang-Shuk;Jang, In-Woo;Lee, Kye-Nam;Lee, Seaung-Suk;Park, Sung-Hyung;Park, Gun-Sook;Ban, Geun-Do;Park, Young-Jin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.3
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    • pp.185-196
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    • 2002
  • MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

Non volatile memory device using mobile proton in gate insulator by hydrogen neutral beam treatment

  • Yun, Jang-Won;Jang, Jin-Nyeong;Hong, Mun-Pyo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.192.1-192.1
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    • 2015
  • We demonstrated the nonvolatile memory functionality of nano-crystalline silicon (nc-Si) and InGaZnOxide (IGZO) thin film transistors (TFTs) using mobile protons that are generated by very short time hydrogen neutral beam (H-NB) treatment in gate insulator (SiO2). The whole memory fabrication process kept under $50^{\circ}C$ (except SiO2 deposition process; $300^{\circ}C$). These devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We also executed hydrogen treatment in order to figure out the difference of mobile proton generation between PECVD and H-NB CVD that we modified. Our study will further provide a vision of creating memory functionality and incorporating proton-based storage elements onto a probability of next generation flexible memorable electronics such as low power consumption flexible display panel.

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Design of a Scalable Systolic Synchronous Memory

  • Jeong, Gab-Joong;Kwon, Kyoung-Hwan;Lee, Moon-Key
    • Journal of Electrical Engineering and information Science
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    • v.2 no.4
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    • pp.8-13
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    • 1997
  • This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

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Forecasting technics for variable frequency control of PWM inverter using one-chip $\mu$-com (One-chip $\mu$-com을 이용한 PWM 인버터의 가변 주파수 제어 추정 기법)

  • Park, Jung-Gyun;Kim, Hyun;Choi, Hyun-Young;Yeo, Duk-Gu;Oh, Se-Ho;Kim, Yang-Mo
    • Proceedings of the KIEE Conference
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    • 2001.07b
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    • pp.1055-1057
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    • 2001
  • The switching circuit of PWM inverter is very complicated. By using one-chip $\mu$-com the complication of switching circuit is possible to be diminished. But because in one-chip $\mu$-com the limitation of processed memory size exists, the switching handling method has to be simple. In this paper, to effectively utilize the switching handling, we presented the estimation method of PWM pulses which is different form the conventional PWM switching method by the comparison.

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Bipolar Resistance Switching Characteristics of $NiO_{1+x}$ films with Adding Higher-Valence Impurities

  • Kim, Jong-Gi;Son, Hyeon-Cheol
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.370-370
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    • 2010
  • The effects of adding higher-valence impurities on the bipolar resistive switching characteristics of Pt/$NiO_{1+x}$/TiN MIM stacks and physical properties were investigated. $NiO_{1+x}$ films with 14% W deposited at 20% oxygen partial pressure exhibited the bipolar resistance switching characteristics in Pt/$NiO_{1+x}$/TiN MIM stacks, while $NiO_{1+x}$ films with 8.2% W show unipolar resistance switching behavior. The relationship of W-doping and the crystallinity was studied by X-ray diffraction. The metallic Ni contents and $WO_x$ binding states with W amount was investigated by XPS. Our result showed that the metallic Ni, $WO_x$ binding states, and crystallinity in $NiO_{1+x}$ played an important role on the bipolar resistive switching.

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