• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.173-181
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• 1992

Tantalum pentoxide($Ta_{2}O_{5}$) thin films on p-type (100) silicon wafer were fabricated by RF reactive sputtering. Physical properties and structure of the specimens were examined by XRD and AES. From the C-V analysis, the dielectric constant of $Ta_{2}O_{5}$ films was in the range of 10-12 in the reactive gas atmosphere in which 10% of oxygen gas is mixed. The ratio of Ta : 0 was 1 : 2 and 1 : 2.49 by AES and RBS examination, respectively. The heat-treatment at $700^{\circ}C$ in $O_{2}$ ambient led to induce crystallization. When the heat-treatment temperature was $1000^{\circ}C$, the dielectric constant was 20.5 in $O_{2}$ ambient and 23 in $N_{2}$ ambient, respectively. The crystal structure of $Ta_{2}O_{5}$ film was pseudo hexagonal of ${\delta}-Ta_{2}O_{5}$. The flat band voltage shift(${\Delta}V_{FB}$) of the specimens and the leakage current density were decreased for higher oxygen mixing ratio. The maximum breakdown field was 2.4MV/cm at the oxygen mixing ratio of 10%. The $Ta_{2}O_{5}$ films will be applicable to hydrogen ion sensitive film and gate oxide material for memory device.

• Journal of the Korean Ceramic Society
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• v.39 no.12
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• pp.1128-1132
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• 2002

$ReMnO_3$(Re:Y, Ho, Er) thin films were prepared by MOCVD method available to non-volatile memory device with MFS-FET structure. $ReMnO_3$ thin films were deposited on the Si(100) substrate at 700${\circ}C$ for 2h. When the films were post-annealed at 900${\circ}C$ for 1h in air, the single phase of hexagonal $ReMnO_3$ thin films were detected. Ferroelectric properties of $ReMnO_3$ thin films were dependent on the degree of c-axis orientation in the single phase of hexagonal structure and remnant polarization (Pr) of $YMnO_3$ thin films with high degree of c-axis orientation was 105 nC/$cm^2$. Leakage current density was dependent on the grain size of microstructure and that of $YMnO_3$ thin films with grain size of 100∼150 nm was $10^{-8}$ A/$cm^2$ at applied voltage of 0.5 V.

• Korean Journal of Materials Research
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• v.11 no.5
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• pp.367-371
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• 2001

In this paper, theS $r_2$(T $a_{1-x}$ , N $b_{x}$)$_2$ $O_{7}$(STNO) films among ferroelectric materials having a low dielectric constant for metal-ferroelectric-semiconductor field effect transistor(MFS-FET) were discussed. The STNO thin films were deposited on p-type Si(100) at room temperature by co-sputtering with S $r_2$N $b_2$ $O_{7(SNO)}$ ceramic target and T $a_2$ $O_{5}$ ceramic target. The composition of STNO thin films was varied by adjusting the power ratios of SNO target and T $a_2$ $O_{5}$ target. The STNO films were annealed at 8$50^{\circ}C$, 90$0^{\circ}C$ and 9$50^{\circ}C$ temperature in oxygen ambient for 1 hour. The value of x has significantly influenced the structure and electrical properties of the STNO films. In the case of x= 0.4, the crystallinity of the STNO films annealed at 9$50^{\circ}C$ was observed well and the memory windows of the Pt/STNO/Si structure were 0.5-8.3 V at applied voltage of 3-9 V and leakage current density was 7.9$\times$10$_{08}$A/$\textrm{cm}^2$ at applied voltage of -5V.of -5V.V.V.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.49-56
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• 2004

The performance of the multiprocessor systems is limited by the several factors. The system performance is affected by the processor speed, memory delay, and interconnection network bandwidth/latency. By the evolution of semiconductor technology, off the shelf microprocessor speed breaks beyond GHz, and the processors can be scalable up to multiprocessor system by connecting through the interconnection networks. In this situation, the system performances are bound by the latencies and the bandwidth of the interconnection networks. SCI, Myrinet, and Gigabit Ethernet are widely adopted as a high-speed interconnection network links for the high performance cluster systems. Performance improvement of the interconnection network can be achieved by the bandwidth extension and the latency minimization. Speed up of the operation clock speed is a simple way to accomplish the bandwidth and latency betterment, while its physical distance makes the difficulties to attain the high frequency clock. Hence the system performance and scalability suffered from the interconnection network limitation. Duplicating the link of the interconnection network is one of the solutions to resolve the bottleneck of the scalable systems. Dual-ring SCI link structure is an example of the interconnection network improvement. In this paper, I propose a network topology and a transaction path algorism, which optimize the latency and the efficiency under the duplicated links. By the simulation results, the proposed structure shows 1.05 to 1.11 times better latency, and exhibits 1.42 to 2.1 times faster execution compared to the dual ring systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.