• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.132-138
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• 2003

We investigated the polarization retention characteristics of ferroelectric capacitors with $Pb(Zr,Ti)O_3$ (PZT) thin films which were fabricated by different deposition methods. In thermally-accelerated retention tests, PZT films which were prepared by a chemical solution deposition (CSD) method showed rapid decay of retained polarization charges as the thickness of the films decreased down to 100 nm, while the films which were grown by metal organic chemical vapor deposition (MOCVD) retained relatively large non-volatile charges at the corresponding thickness. We concluded that in the CSD-grown films, the thicker interfacial passive layer compared with the MOCVD-grown films had an unfavorable effect on retention behavior. We observed the existence of such interfacial layers by extrapolation of the total capacitance with thickness of the films and the capacitance of these layers was larger in MOCVD-grown films than in CSD-grown films. Due to incomplete compensation of surface polarization charges by the free charges in the metal electrodes, the interfacial field activated the space charges inside the interfacial layers and deposited them at the boundary between the ferroelectric layer and the interfacial layer. Such space charges built up an internal field inside the films, which interfered with domain wall motion, so that retention property at last became degraded. We observed less imprint which was a result of less internal field in MOCVD-grown films while large imprint was observed in CSD-grown films.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12B
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• pp.831-837
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• 2005

Personal general purpose computer(PC) has been evolved from desktop to portable mobile device such as tablet PC and PDA. Technology innovation on semiconductor have made it possible to package a reasonably Powerful Processor and memory subsystem with advanced input/output devices. At last these subsystems are miniaturized into wearable system. Wearable computer has recently gained attention as the post PC in the ubiquitous environment. Wearable computing becomes more and more feasible and receives growing attention throughout industry and the consumer marketplaces. This paper proposed and developed WPS that has multimedia features and network features as a wearable embedded platform. We explain the form, overall architecture, functions and user applications of this WPS. This paper also discusses the form of next generation computer platform with intuitive user interfaces and well designed applications in the future.

• Fire Science and Engineering
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• v.13 no.3
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• pp.19-26
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• 1999

$CO_2$ extinguishing system is the most $\phi$pular among the gas extinguishing system. $CO_2$ is usually stored with liquified state. But, it gasifies at the tip of nozzle when $CO_2$ was released through the pipe and head. A ro$\alpha$n temperature is very low when $CO_2$ was released. So electrical instrument, magnetic storage equipment and memory semiconductor are electrically or physically injured by cooling effect in a few minutes. So, we intend to find out temperature profile and electrical damage in compartment area, and supply basic d data for research and making standards and code through the full scale experiment. As result of experiment on the damage due to cooling effect from $CO_2$ extinguishing system, i instantaneous discharging temperature. was $-82.5^{\circ}C$ in average. An average temp. in the compartment after discharging $CO_2$ was $-40^{\circ}C$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.181-186
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• 2015

With the rapid growth of semiconductor technologies, small-sized devices with powerful computing abilities are becoming a reality. As this environment has a limit on power supply, NVM storage that has a high density and low power consumption is preferred to HDD or SSD. However, legacy software layers optimized for HDDs should be revisited. Specifically, as storage performance approaches DRAM performance, existing I/O mechanisms and software configurations should be reassessed. This paper explores the challenges and implications of using NVM storage with a broad range of experiments. We measure the performance of a system with NVM storage emulated by DRAM with proper timing parameters and compare it with that of HDD storage environments under various configurations. Our experimental results show that even with storage as fast as DRAM, the performance gain is not large for read operations as current I/O mechanisms do a good job hiding the slow performance of HDD. To assess the potential benefit of fast storage media, we change various I/O configurations and perform experiments to quantify the effects of existing I/O mechanisms such as buffer caching, read-ahead, synchronous I/O, direct I/O, block I/O, and byte-addressable I/O on systems with NVM storage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.43-50
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• 2016

NAND flash based storage devices adopts multi-channel and multi-way architecture to improve performance using parallel operation of multiple NAND devices. However, multiple NAND devices consume higher current and peak power overlap problem influences on the system stability and data reliability. In this paper, current waveform is measured for erase, program and read operations, peak current and model is defined by profiling method, and estimated probability of peak current overlap among NAND devices. Also, system level TLM simulator is developed to analyze peak overlap phenomenon depending on various simulation scenario. In order to remove peak overlapping, token-ring based simple power management method is applied in the simulation experiments. The optimal peak overlap ratio is proposed to minimize performance degradation based on relationship between peak current overlapping and system performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.36-42
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• 2016

In multi-level-cell based storage devices, TLC NAND has been employed solid state drive due to cost effectiveness. Since TLC has slow performance and low endurance compared with MLC, TLC based storage has adopted SLC buffer scheme to improve performance. To improve SLC buffer scheme, this paper proposes page overwriting method in SLC block. This method provides data updates without erase operation within a limited number. When SLC buffer area is filled up, FTL should execute copying valid pages and erasing it. The proposed method reduces erase counts by 50% or more compared with previous SLC buffer scheme. Simulation results show that the proposed SLC buffer overwrite method achieves 2 times write performance improvement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.22.2-22.2
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• 2009

Currently, metal silicides become increasingly more essential part as a contact material in complimentary metal-oxide-semiconductor (CMOS). Among various silicides, NiSi has several advantages such as low resistivity against narrow line width and low Si consumption. Generally, metal silicides are formed through physical vapor deposition (PVD) of metal film, followed by annealing. Nanoscale devices require formation of contact in the inside of deep contact holes, especially for memory device. However, PVD may suffer from poor conformality in deep contact holes. Therefore, Atomic layer deposition (ALD) can be a promising method since it can produce thin films with excellent conformality and atomic scale thickness controllability through the self-saturated surface reaction. In this study, Ni thin films were deposited by thermal ALD using bis(dimethylamino-2-methyl-2-butoxo)nickel [Ni(dmamb)2] as a precursor and NH3 gas as a reactant. The Ni ALD produced pure metallic Ni films with low resistivity of 25 $\mu{\Omega}cm$. In addition, it showed the excellent conformality in nanoscale contact holes as well as on Si nanowires. Meanwhile, the Ni ALD was applied to area-selective ALD using octadecyltrichlorosilane (OTS) self-assembled monolayer as a blocking layer. Due to the differences of the nucleation on OTS modified surfaces toward ALD reaction, ALD Ni films were selectively deposited on un-coated OTS region, producing 3 ${\mu}m$-width Ni line patterns without expensive patterning process.

• Korean Journal of Materials Research
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• v.10 no.11
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• pp.749-764
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• 2000

Amorphous TaSiN thin films of about 90 nm thick were deposited onto poly-Si and $SiO_2/Si$ substrates by rf magnetron sputtering method. TaSiN films exhibited amorphous phase with no crystllization up to $900^{\circ}C$ in oxygen ambient. The penetration depth of oxygen diffusion increased with increasing annealing temperature in oxygen ambient and reached 20 nm deep in a $Ta_{23}Si_{29}N_{48}$ layer at $600^{\circ}C$ for 30min. The resistivity of as-deposited $Ta_{23}Si_{29}N_{48}$ thin films was about $1,300{\mu}{\Omega}-cm$, however those of annealed films markedly increased above $700^{\circ}C$ in oxygen ambient as the annealing temperature increased.