• Title/Summary/Keyword: memory retention

Search Result 258, Processing Time 0.022 seconds

Effects of Emotion on Color Vividness of Visual Memory (감성이 시각적 이미지의 색감기억에 미치는 영향)

  • Jang, Phil-Sik
    • Journal of the Ergonomics Society of Korea
    • /
    • v.30 no.1
    • /
    • pp.221-227
    • /
    • 2011
  • Objective: The aim of this study is to investigate the quantitative effects of various emotions and retention periods on the color vividness of visual memory. Background: Although numerous studies have focused on the effects of emotions on memory such as visual detail and vividness of emotional events compared to neutral events, the relationship between emotion and visual memory is ambiguous yet. Furthermore, there were few studies on the effect of emotion on vividness of visual memory. Method: A total of 68 subjects were participated in serial experiments proceed on online and the experiments had two phases: recognition phase and reproduction phase. The 15 photographs were used as visual stimuli and all experiments were conducted over the internet(experiment website) and the results were collected on the web database. Results: The retention period, sleep-arousal emotion and subjective saturation of visual stimuli had a significant effect on the color vividness of visual memory. Conclusion: The results suggested that the color of visual stimulus might be more vividly remembered when it is arousing, the subjective saturation is higher and the retention period is longer. Application: The findings of this study may help clarify the relationship between human emotions and visual memory.

Simulation and Modelling of the Write/Erase Kinetics and the Retention Time of Single Electron Memory at Room Temperature

  • Boubaker, Aimen;Sghaier, Nabil;Souifi, Abdelkader;Kalboussi, Adel
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.10 no.2
    • /
    • pp.143-151
    • /
    • 2010
  • In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.

Write-in and Retention Characteristics of Nonvolatile MNOS Memory Devices (비휘발성 MNOS기억소자의 기억 및 유지특성)

  • 이형옥;강창수;이상배;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 1991.10a
    • /
    • pp.44-47
    • /
    • 1991
  • Electron injection and memory retention chracteristics of the MNOS devices with thin oxide layer of 23${\AA}$ thick and silicon nitride layer of 1000${\AA}$ thick which are fabricated for this experiment. As a result, pulse amplitude increase oxide current is dominated in linearly increasing region of $\Delta$V$\_$FB/the decreasing region after saturation was due to the increased silicon nirtide current. In low pulse ampiltude $\Delta$V$\_$FB/ is not variated on temperature, but as temperature and pulse amplitude increase. $\Delta$V$\_$FB/ is decreased after saturation. And the decay rate during 10$^4$sec after electron injection was ohiefly dominated by the back tunneling of emission from memory trap to silicon. Memory retention characteristics in V$\_$FB/ stage was better than that of OV retention regardless of injection conditions.

Forgetting based File Cache Management Scheme for Non-Volatile Memory (데이터 망각을 활용한 비휘발성 메모리 기반 파일 캐시 관리 기법)

  • Kang, Dongwoo;Choi, Jongmoo
    • Journal of KIISE
    • /
    • v.42 no.8
    • /
    • pp.972-978
    • /
    • 2015
  • Non-volatile memory (NVM) supports both byte addressability and non-volatility. These characteristics make it feasible for NVM to be employed at any layer of the memory hierarchy such as cache, memory and disk. An interesting characteristic of NVM is that, even though it supports non-volatility, its retention capability is limited. Furthermore NVM has tradeoff between its retention capability and write latency. In this paper, we propose a novel NVM-based file cache management scheme that makes use of the limited retention capability to improve the cache performance. Experimental results with real-workloads show that our scheme can reduce access latency by up to 31% (24.4% average) compared with the conventional LRU based cache management scheme.

Memory retention of mathematical concepts in multiplication in the inquiry-based pantomime instruction (탐구 중심 판토마임 교수에서 곱셈 개념의 기억의 보존)

  • Bae, Jong-Soo;Park, Do-Yong;Park, Man-Goo
    • School Mathematics
    • /
    • v.9 no.4
    • /
    • pp.507-521
    • /
    • 2007
  • The purpose of this study was to investigate the effects of memory retention of mathematical concepts in multiplication in the inquiry-based pantomime instructions. Three months later after the pre-test, a comparison was made between traditional class (TC) and class with the inquiry-based pantomime (IP) approach in terms of students retention of mathematical understandings. Results of the study indicated that the If instructions promoted effective long-term retention of knowledge. We concluded that instructional strategies that promoted active engagement in learning using life examples and drawings produced effective long-term retention of knowledge.

  • PDF

Robustness of Differentiable Neural Computer Using Limited Retention Vector-based Memory Deallocation in Language Model

  • Lee, Donghyun;Park, Hosung;Seo, Soonshin;Son, Hyunsoo;Kim, Gyujin;Kim, Ji-Hwan
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • v.15 no.3
    • /
    • pp.837-852
    • /
    • 2021
  • Recurrent neural network (RNN) architectures have been used for language modeling (LM) tasks that require learning long-range word or character sequences. However, the RNN architecture is still suffered from unstable gradients on long-range sequences. To address the issue of long-range sequences, an attention mechanism has been used, showing state-of-the-art (SOTA) performance in all LM tasks. A differentiable neural computer (DNC) is a deep learning architecture using an attention mechanism. The DNC architecture is a neural network augmented with a content-addressable external memory. However, in the write operation, some information unrelated to the input word remains in memory. Moreover, DNCs have been found to perform poorly with low numbers of weight parameters. Therefore, we propose a robust memory deallocation method using a limited retention vector. The limited retention vector determines whether the network increases or decreases its usage of information in external memory according to a threshold. We experimentally evaluate the robustness of a DNC implementing the proposed approach according to the size of the controller and external memory on the enwik8 LM task. When we decreased the number of weight parameters by 32.47%, the proposed DNC showed a low bits-per-character (BPC) degradation of 4.30%, demonstrating the effectiveness of our approach in language modeling tasks.

Integration Process and Reliability for $SrBi_2$ $Ta_2O_9$-based Ferroelectric Memories

  • Yang, B.;Lee, S.S.;Kang, Y.M.;Noh, K.H.;Hong, S.K.;Oh, S.H.;Kang, E.Y.;Lee, S.W.;Kim, J.G.;Shu, C.W.;Seong, J.W.;Lee, C.G.;Kang, N.S.;Park, Y.J.
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.1 no.3
    • /
    • pp.141-157
    • /
    • 2001
  • Highly reliable packaged 64kbit ferroelectric memories with $0.8{\;}\mu\textrm{m}$ CMOS ensuring ten-year retention and imprint at 125^{\circ}C$ have been successfully developed. These superior reliabilities have resulted from steady integration schemes free from the degradation, due to layer stress and attacks of process impurities. The resent results of research and development for ferroelectric memories at Hynix Semiconductor Inc. are summarized in this invited paper.

  • PDF

Boundary Contraction for Wide-Angle Images on Monitor Screen: An Effect of Retention Interval (파지기간에 따른 모니터 화면상 광각이미지의 경계축소현상)

  • Jang, Phil-Sik
    • Journal of the Korea Society of Computer and Information
    • /
    • v.12 no.4
    • /
    • pp.61-68
    • /
    • 2007
  • Two experiments examined the visual memory distortion by presenting 170 subjects with wide-angle views of four scenes on monitor screen. Retention interval of 0, 1 and 48 hours tested in reproduction and recognition experiment. The results of reproduction showed that the subjects tend to magnify the foreground and background of scenes compared to the real input (scene) for all retention intervals. The viewers recognized mure wide-angle views for the same scenes at the retention interval of 1 and 48 hours. These results demonstrated boundary extension is not a robust and unidirectional phenomenon but boundary contraction can be occurred with wide-angle views. The results also suggested that boundary contraction is the product of the activation of a memory schema hypothesis: In memory the representation moves toward a prototypical view and prototypical object size.

  • PDF

Charge Spreading Effect of Stored Charge on Retention Characteristics in SONOS NAND Flash Memory Devices

  • Kim, Seong-Hyeon;Yang, Seung-Dong;Kim, Jin-Seop;Jeong, Jun-Kyo;Lee, Hi-Deok;Lee, Ga-Won
    • Transactions on Electrical and Electronic Materials
    • /
    • v.16 no.4
    • /
    • pp.183-186
    • /
    • 2015
  • This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.