• Journal of the Korea Society of Computer and Information
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• v.14 no.2
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• pp.45-57
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• 2009

ETexture mapping is a technique used for adding reality to an image in 3D graphics. However. this technique becomes the bottleneck of the 3D graphics pipeline because it requires large processing power and high memory bandwidth. For reducing memory latency in texture mapping, texture cache is used. As portable devices become smaller and they have power constraint, it is important to reduce the area and the power consumption of the texture cache. In this paper we propose using a small texture cache to reduce the area and the power consumption of the texture cache. Furthermore, we propose techniques to keep a performance comparable to large texture caches by using prefetch techniques and a victim cache. Simulation results show the proposed small texture cache can reduce the area and the power consumption up to 70% and 60%, respectively, by using $1{\sim}2K$ bytes texture cache compared to the conventional 16K bytes cache while keeping the performance.

• Journal of the Korea Society of Computer and Information
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• v.29 no.6
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• pp.1-12
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• 2024

Deep learning with faster and more accurate results requires large amounts of storage space and large computations. Accordingly, many studies are using hardware accelerators for quick and accurate calculations. However, the performance bottleneck is due to data movement between the hardware accelerators and the CPU. In this paper, we propose a data prefetch strategy that can efficiently reduce such operational bottlenecks. The core idea of the data prefetch strategy is to predict the data needed for the next task and upload it to local memory while the hardware accelerator (Matrix Multiplication Unit, MMU) performs a task. This strategy can be enhanced by using a dual buffer to perform read and write operations simultaneously. This reduces latency and execution time of data transfer. Through simulations, we demonstrate a 24% improvement in the performance of hardware accelerators by maximizing parallel processing with dual buffers and bottlenecks between memories with data prefetch.

• Sleep Medicine and Psychophysiology
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• v.12 no.2
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• pp.122-132
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• 2005

Objectives: The objective of this study is to assess cognitive functions and their relationship with sleep symptoms in young narcoleptic patients. Methods: Eighteen young narcolepsy patients and 18 normal controls (age: 17-35 years old) were recruited. All narcolepsy patients had HLA $DQB_1$ *0602 allele and cataplexy. Several important areas of cognition were assessed by a battery of neuropsychological tests consisting of 13 tests: executive functions (e.g. cognitive set shifting, inhibition, and selective attention) through Wisconsin card sorting test, Trail Making A/B, Stroop test, Ruff test, Digit Symbol, Controlled Oral Word Association and Boston Naming Test; alertness and sustained attention through paced auditory serial addition test; verbal/nonverbal short-term memory and working memory through Digit Span and Spatial Span; visuospatial memory through Rey-Osterrieth complex figure test; verbal learning and memory through California verbal learning test; and fine motor activity through grooved pegboard test. Sleep symptoms in narcolepsy patients were assessed with Epworth sleepiness scale, Ullanlinna narcolepsy scale, multiple sleep latency test, and nocturnal polysomnography. Relationship between cognitive functions and sleep symptoms in narcolepsy patients was also explored. Results: Compared with normal controls, narcolepsy patients showed poor performance in paced auditory serial addition (2.0 s and 2.4 s), digit symbol tests, and spatial span (forward)(t=3.86, p<0.01; t=-2.47, p=0.02; t=-3.95, p<0.01; t=-2.22, p=0.03, respectively). There were no significant between-group differences in other neuropsychological tests. In addition, results of neuropsychological test in narcolepsy patients were not correlated with Epworth sleepiness scale score, Ullanlinna narcolepsy scale score and sleep variables in multiple sleep latency test or nocturnal polysomnography. Conclusion: The current findings suggest that young narcolepsy patients have impaired attention. In addition, impairment of attention in narcolepsy might not be solely due to sleep symptoms such as excessive daytime sleepiness.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.49-56
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• 2004

The performance of the multiprocessor systems is limited by the several factors. The system performance is affected by the processor speed, memory delay, and interconnection network bandwidth/latency. By the evolution of semiconductor technology, off the shelf microprocessor speed breaks beyond GHz, and the processors can be scalable up to multiprocessor system by connecting through the interconnection networks. In this situation, the system performances are bound by the latencies and the bandwidth of the interconnection networks. SCI, Myrinet, and Gigabit Ethernet are widely adopted as a high-speed interconnection network links for the high performance cluster systems. Performance improvement of the interconnection network can be achieved by the bandwidth extension and the latency minimization. Speed up of the operation clock speed is a simple way to accomplish the bandwidth and latency betterment, while its physical distance makes the difficulties to attain the high frequency clock. Hence the system performance and scalability suffered from the interconnection network limitation. Duplicating the link of the interconnection network is one of the solutions to resolve the bottleneck of the scalable systems. Dual-ring SCI link structure is an example of the interconnection network improvement. In this paper, I propose a network topology and a transaction path algorism, which optimize the latency and the efficiency under the duplicated links. By the simulation results, the proposed structure shows 1.05 to 1.11 times better latency, and exhibits 1.42 to 2.1 times faster execution compared to the dual ring systems.

• Animal cells and systems
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• v.7 no.4
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• pp.303-307
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• 2003

The aim of this study is to investigate whether alcohol alters learning and memory processes pertaining to emotional and spatial factors using the active avoidance and T-maze task in zebrafish. In the active avoidance task, zebrafish were trained to escape from one compartment to another to avoid electric shocks (unconditioned stimulus) following a conditioned light signal. Acquisition of active avoidance task appeared to be normal in zebrafish that were treated with 1% alcohol for 30 min for 17 days until the end of the behavioral test, and retention ability of learned behavior, tested 2 days later, was the same as control group. In the T-maze task, the time to find a reservoir was compared. While the latency was similar during the 1 st training session between control and alcohol-treated zebrafish, it was significantly longer in alcohol-treated zebrafish during retention test 24 h later. Furthermore, when alcohol was treated 30 min after 2nd session without prior treatment, zebrafish demonstrated similar retention ability compared to control. These results suggest that chronic alcohol treatment alters spatial learning of zebrafish, but not emotional learning.

• Journal of Information Technology Services
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• v.12 no.4
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• pp.369-380
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• 2013

The advent of the state-of-the-art technologies such as cloud computing and big data processing stimulates the provision of various new IT services, which implies that more servers are required to support them. However, the need for more servers will lead to more energy consumption and the efficient use of energy in the computing environment will become more important. The next generation nonvolatile RAM has many desirable features such as byte addressability, low access latency, high density and low energy consumption. There are many approaches to adopt them especially in the area of the file system involving storage devices, but their focus lies on the improvement of system performance, not on energy reduction. This paper suggests a novel approach for energy reduction in which the MRAM-based SSD is utilized as a storage device instead of the hard disk and a downsized page is adopted instead of the 4KB page that is the size of a page in the ordinary file system. The simulation results show that energy efficiency of a new approach is very effective in case of accessing the small number of bytes and is improved up to 128 times better than that of NAND Flash memory.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.6
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• pp.3208-3229
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• 2017

Rectification is an essential procedure for simplifying the disparity extraction of stereo matching algorithms by removing vertical mismatches between left and right images. To support real-time stereo matching, studies have introduced several look-up table (LUT)- and computational logic (CL)-based rectification approaches. However, to support high-resolution images, the LUT-based approach requires considerable memory resources, and the CL-based approach requires numerous hardware resources for its circuit implementation. Thus, this paper proposes a multi-level accumulation-based rectification method as a simple CL-based method and its circuit implementation. The proposed method, which includes distortion correction, reduces addition operations by 29%, and removes multiplication operations by replacing the complex matrix computations and high-degree polynomial calculations of the conventional rectification with simple multi-level accumulations. The proposed rectification circuit can rectify $1,280{\times}720$ stereo images at a frame rate of 135 fps at a clock frequency of 125 MHz. Because the circuit is fully pipelined, it continuously generates a pair of left and right rectified pixels every cycle after 13-cycle latency plus initial image buffering time. Experimental results show that the proposed method requires significantly fewer hardware resources than the conventional method while the differences between the results of the proposed and conventional full rectifications are negligible.

• The Korea Journal of Herbology
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• v.22 no.2
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• pp.127-135
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• 2007

Objective : Investigation of the anti-stress effects of Sihosogansan Methods : Passive avoidance test(PAT) was performed after applying immobilization stress in water to rats. Also, forced swimming test(FST) was performed to another rats and after FST, the degree of Tyrosine Hydroxylase(TH) expression was measured with immunohistochemical method in the regions of locus coeruleus(LC) and ventral tegmental area (VTA). Results : In the PAT after immobilization stress in water, response latency was significantly increased in the Sihosogansan(400mg/kg) group in comparison with the control group. In the FST, immobility was significantly decreased in the Sihosogansan groups (100mg/kg, 400mg/kg), comparing with the control group. Stress-induced TH increases were suppressed in the Sihosogansan groups (100mg/kg, 400mg/kg) at the LC and the VTA region respectively. Conclusion : Sihosogansan can improve memory ability of rats, reduce behavior of depression in rats, decrease TH-immunoreactive cells at the LC and VTA region in rat, and it may be concluded that Sihosogansan has significant effect in reducing stress.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.727-729
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• 2005

현재 3차원 그래픽 가속기에서 성능 향상에 대한 문제점으로 대두되고 있는 것은 실제 화면에 그려지는 정보가 저장되는 프레임버퍼에 대한 접근 지연이다. 따라서 본 논문은 기존 픽셀 캐쉬가 포함된 래스터라이져 구조에서 캐쉬 읽기 접근 실패 시 발생하는 패널티와 이에 따른 프레임버퍼에 대한 지연이 발생하는 문제점을 개선하고자, 기존 래스터라이져를 래스터라이져와 합성기로 구분하고 그 사이에 캐쉬 읽기 접근 실패 시 프레임 버퍼에서 정보를 읽어오지 않는 깊이 캐쉬와 색상 캐쉬가 쌍을 이룬 픽셀 캐쉬 메모리 시스템으로 구성된 개선된 3차원 그래픽 가속기 구조을 제안하고 실험을 수행하였다. 실험 결과 제안하는 3차원 그래픽 가속기 구조가 기존 구조에 비해 캐쉬 접근 실패율이 약 $23\%$ 감소하였으며, 평균 메모리 접근 사이클이 $10\%-13\%$ 감소하였으며 이는 상당수의 프레임버퍼에 대한 접근 지연을 감소시킨 것이다. 합성기와 메모리 간의 대역폭은 약 $10\%$ 증가하지만 파이프라인의 작업에는 영향을 미치지는 않는다.

• Sleep Medicine and Psychophysiology
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• v.1 no.1
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• pp.36-46
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• 1994

The event-related potentials are difined as the changes in voltage that occur at paticular time before, during and after something that happens in the physical world or some psychological processes. The possibilities of clinical applications of ERP are considered because the endogenous potentials such as P3 and contingent negative variation(CNV) are determined by the psychological significance of the stimulus. The P3 is a positive wave that occurs when a subject detects an informative task-relevant stimulus. The P3 amplitude and latency are affected by the various factors as subjective probabilites, stimulus meaning and information transmission. It is suggested that P3 wave is associated with the decision making, cognitive or perceptual closure, memory updating and transfer of information to consciousness etc. Although the intracerebral origin of the P3 wave is not known, the P3 may have multiple intracerebral generators. The CNV is a slow potential shift occuring during the foreperiod, between warning and response signals, in a reaction time experiment. It is related to expectancy, preparation etc. The abnormal findings of P3 wave and CNV in various psychiatric disorders are also discussed.