• 제목/요약/키워드: memory latency

검색결과 361건 처리시간 0.031초

스코폴라민으로 유도된 기억력 손상에 대한 복신의 보호 효과 및 작용기전 연구 (Effect of Poria Cocos on the Scopolamine-induced Memory Impairment and Its Underlying Molecular Mechanism)

  • 제갈경환;박성준;김창열;이찬;박종현;장정희
    • 동의생리병리학회지
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    • 제24권2호
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    • pp.228-235
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    • 2010
  • This study was performed to investigate the memory enhancing effect of Poria cocos Wolf (Hoelen cum radix) against scopolamine-induced amnesia in Sprague-Dawley (SD) rats. To induce amnesia, scopolamine (0.75 mg/kg) was intraperitonically injected into SD rats 30 min before starting behavior tests. We have conducted Morris water-maze and Y-maze tests to monitor learning and memory functions. Poria cocos effectively reversed scopolamine-induced memory impairment in SD rats which was represented by an improvement of mean escape latency in water-maze test and spontaneous alterations in Y-maze test. To elucidate possible molecule mechanism, we have measured mRNA as well as protein expression of acetylcholine esterase (AchE), choline acetyltransferase (ChAT), muscarinic acetylcholine receptor (mAchR), and brain-derived neurotrophic factor (BDNF) using RT-PCR and Western blot analysis, respectively. Poria cocos increased mRNA levels of ChAT and mAchR in rat hippocampus compared with those in the scopolamine-injected amnesic group. In addition, protein expression of ChAT and BDNF was also elevated by Poria cocos intake. Furthermore, as an upstrem regulator, the activation of cAMP response element-binding protein (CREB) was assessed by immunohistochemistry. In this immunohistochemical analysis, the phosphorylation of CREB (p-CREB) was reduced by scopolamine injection, which was restored back to control levels by administration of Poria cocos. These results suggest that Poria cocos may improve memory and cognitive deficit in amnesia and have therapeutic potentials through up-regulation of ChAT, mAchR, and BDNF, which seemed to be mediated by activation of CREB.

Effects of ginseol k-g3, an Rg3-enriched fraction, on scopolamine-induced memory impairment and learning deficit in mice

  • Pena, Ike Dela;Yoon, Seo Young;Kim, Hee Jin;Park, Sejin;Hong, Eun Young;Ryu, Jong Hoon;Park, Il Ho;Cheong, Jae Hoon
    • Journal of Ginseng Research
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    • 제38권1호
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    • pp.1-7
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    • 2014
  • Background: Although ginsenosides such as Rg1, Rb1 and Rg3 have shown promise as potential nutraceuticals for cognitive impairment, their use has been limited due to high production cost and low potency. In particular, the process of extracting pure Rg3 from ginseng is laborious and expensive. Methods: We described the methods in preparing ginseol k-g3, an Rg3-enriched fraction, and evaluated its effects on scopolamine-induced memory impairment in mice. Results: Ginseol k-g3 (25-200 mg/kg) significantly reversed scopolamine-induced cognitive impairment in the passive avoidance, but not in Y-maze testing. Ginseol k-g3 (50 and 200 mg/kg) improved escape latency in training trials and increased swimming times within the target zone of the Morris water maze. The effect of ginseol k-g3 on the water maze task was more potent than that of Rg3 or Red ginseng. Acute or subchronic (6 d) treatment of ginseol k-g3 did not alter normal locomotor activity of mice in an open field. Ginseol k-g3 did not inhibit acetylcholinesterase activity, unlike donezepil, an acetylcholinesterase inhibitor. Rg3 enrichment through the ginseol k-g3 fraction enhanced the efficacy of Rg3 in scopolamine-induced memory impairment in mice as demonstrated in the Morris water maze task. Conclusion: The effects of ginseol k-g3 in ameliorating scopolamine-induced memory impairment in the passive avoidance and Morris water maze tests indicate its specific influence on reference or long-term memory. The mechanism underlying the reversal of scopolamine-induced amnesia by ginseol k-g3 is not yet known, but is not related to anticholinesterase-like activity.

기면병 환자의 인지기능 평가 (Evaluation of Cognitive Functions in Patients with Narcolepsy)

  • 진유양;윤진상;정은경
    • 농촌의학ㆍ지역보건
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    • 제38권2호
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    • pp.97-107
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    • 2013
  • 기면병 환자들은 과도한 주간 졸음증, 탈력발작, 수면마비, 입면시 환각 외에도 야간 수면의 장애를 가지고 있다는 것을 알 수 있었다. 주의, 기억 그리고 집행에 대한 인지기능을 평가한 결과 d2 의 경우 전체 수행을 한 총 넘버수, 지속적이 수행이 요구되는 과제인 정반응 수(TN-E), 집중력 지표(CP), 그리고 과제를 수행하는데 일관성과 안정성을 평가하는 변동률(FR)에서 기면병 환자군의 점수가 대조군에 비해 통계적으로 유의하게 낮았다. 이는 기면병 환자의 주의력에 결함을 시사한다. 또한, K-CVLT 검사의 B 목록의 경우 기면병 환자군에서 대조군에 비하여 저조한 수행을 보여 언어성 주의력에 저하를 시사한다. 무엇인가를 기억하기 위해서는 한 가지에 주의를 기울여야 하기 때문에 주의와 기억은 밀접하게 관련되어 있으므로 주의력은 기억이나 집행기능 등의 상위인지기능의 수행에도 영향을 줄 수 있다. 따라서 기면병 환자들에서 기존에 보고되었던 주의력 이외의 인지기능 저하는 실제로 주의력 저하에 의한 이차적인 현상으로도 생각해 볼 수 있다. 기면병은 개인의 삶의 질적인 측면뿐 아니라, 인지기능 저하로 인해 사고가 증가시킨다는 점은 공중보건학적으로도 중요한 문제임에도 불구하고[26], 기면병 환자의 주의, 기억, 그리고 집행에 대한 인지기능을 포괄적으로 평가하는 연구는 거의 이루어지지 않았다. 이 연구는 기면병 환자에서 주의, 기억 그리고 집행기능에 대한 포괄적인 신경심리검사를 통하여 인지기능을 평가하였고, 인지기능의 재활 및 개선을 위한 유용한 자료로서 의의가 있다.

NUMA 시스템 가상화 환경에서 메모리 접근 지연을 줄이기 위한 VCPU 스케줄링 기법 (A NUMA-aware VCPU Scheduling for Reducing Memory Access Latency in Virtualized Environments)

  • 김정훈;김지홍;엄영익
    • 한국정보과학회:학술대회논문집
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    • 한국정보과학회 2012년도 한국컴퓨터종합학술대회논문집 Vol.39 No.1(A)
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    • pp.265-267
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    • 2012
  • 최근 들어, 하드웨어 플랫폼은 다수의 코어 아키텍처의 메모리 대역폭을 유지하기 위해 NUMA 구조로 설계되고 있다. 이러한 NUMA 시스템 구조에서 다른 노드의 메모리에 접근할 경우, 더 많은 시간과 비용이 소모된다. 따라서 이를 고려한 스케줄링 기법들이 가상화 혹은 가상화되지 않은 시스템 환경에서 연구되고 있다. 하지만, 아직까지 NUMA 시스템 가상화 환경에서 리모트 접근을 제거함과 동시에 이에 따른 오버헤드를 최소화하는 연구는 없었다. 따라서 본 논문에서는 이러한 환경에서 메모리 접근 지연을 줄이기 위한 VCPU 스케줄링 기법을 제안한다. 본 기법은 노드별 페이지 테이블 관리, LRU 기반 게스트 스케줄러, 캐시 오염 태스크 전용 버퍼 관리 기술을 이용한다. 다른 기법들과의 비교 및 분석 결과에서 알 수 있듯이, 본 기법을 적용할 경우 NUMA 시스템 노드 간 리모트 접근을 없애고, 이에 따른 오버헤드를 최소화하며, 주어진 하드웨어 캐시를 효율적으로 사용할 수 있다.

처리 프레임의 재구성을 통한 효율적인 MCTF 구조 (An Efficient MCTF Architecture using Processing Frame Re-configuration)

  • 서영호;최현준;김영현;김동욱
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.335-338
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    • 2005
  • In this paper, we proposed a new MCTF (Motion Compensated Temporal Filtering) technique and its hardware (H/W) architecture for SVC (Scalable Video Coding). Since the proposed MCTF Kernel has a extensible architecture, it executes temporal filtering using (5,3) and (3,1) lifting operation. Also it has the same output data rate as the input, and it can continuously produce filtered frames after some latency time. Since the proposed architecture has simpler architecture than previous ones, it is easily mapped into H/W and has optimized memory usage rate and low cost.

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Efficient Parallel Block-layered Nonbinary Quasi-cyclic Low-density Parity-check Decoding on a GPU

  • Thi, Huyen Pham;Lee, Hanho
    • IEIE Transactions on Smart Processing and Computing
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    • 제6권3호
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    • pp.210-219
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    • 2017
  • This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

Sort-Last 병렬 렌더링을 위한 효과적인 메모리 프로세서 구조 (A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering)

  • 윤덕기;김경수;이경호;박우찬
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2006년도 춘계학술발표대회
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    • pp.1363-1366
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    • 2006
  • 본 논문에서는 각각의 그래픽 가속기에 픽셀 캐시를 사용가능 하게 하면서 성능을 증가시키고 일관성 문제를 해결하는 병렬 렌더링 프로세서를 제안한다. 제안하는 구조에서는 픽셀 캐시 미스에 의한 latency를 감소시켰다. 이러한 2가지 성과를 위하여 현재의 새로운 픽셀 캐시 구조에 효과적인 메모리 구조를 포함시켰다. 실험 결과는 제안하는 구조가 16개 이상의 레스터라이저에서 거의 선형적으로 속도 향상을 가져옴을 보여준다..

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Simulation-based Design Verification for High-performance Computing System

  • Jeong Taikyeong T.
    • 한국멀티미디어학회논문지
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    • 제8권12호
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    • pp.1605-1612
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    • 2005
  • This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

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UML을 이용한 지그비 어플리케이션모델개발에 관한 연구 (A Study on ZigBee Application Model Development using UML)

  • 정승모;유주형;임동진
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2009년도 제40회 하계학술대회
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    • pp.1814_1816
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    • 2009
  • ZigBee is a technology that is being rapidly developed since its power consumption is low and the stability of its communication is high. However, documented data which is coded using conventional programming languages such as C or assembly programming language would not be able to fulfill the various requirements upon application development by ZigBee. Unified Modelling Languge (UML) could be one of the alternatives to solve this problem. UML provides a variety of diagrams by which the results of the software development can be presented visually and by which the developers can communicate more spontaneously. This paper shows the results of an ongoing study into the application of model-driven methods for ZigBee Application. Also, this paper shows that this approach is feasible by comparing memory usage, latency, and power consumption of UML modelling code with those of handwritten code.

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내장형 32비트 RISC 콘트롤러의 VLSI 구현 (A VLSI implementation of 32-bit RISC embedded controller)

  • 이문기;최병윤;이승호
    • 전자공학회논문지A
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    • 제31A권10호
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    • pp.141-151
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    • 1994
  • this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

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