• Title/Summary/Keyword: memory interface

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Design of Integrated Management System for Electronic Library Based on SaaS and Web Standard

  • Lee, Jong-Hoon;Min, Byung-Won;Oh, Yong-Sun
    • International Journal of Contents
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    • v.11 no.1
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    • pp.41-51
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    • 2015
  • Management systems for electronic library have been developed on the basis of Client/Server or ASP framework in domestic market for a long time. Therefore, both service provider and user suffer from their high cost and effort in management, maintenance, and repairing of software as well as hardware. Recently in addition, mobile devices like smartphone and tablet PC are frequently used as terminal devices to access computers through the Internet or other networks, sophisticatedly customized or personalized interface for n-screen service became more important issue these days. In this paper, we propose a new scheme of integrated management system for electronic library based on SaaS and Web Standard. We design and implement the proposed scheme applying Electronic Cabinet Guidelines for Web Standard and Universal Code System. Hosted application management style and software on demand style service models based on SaaS are basically applied to develop the management system. Moreover, a newly improved concept of duplication check algorithm in a hierarchical evaluation process is presented and a personalized interface based on web standard is applied to implement the system. Algorithms of duplication check for journal, volume/number, and paper are hierarchically presented with their logic flows. Total framework of our development obeys the standard feature of Electronic Cabinet Guidelines offered by Korea government so that we can accomplish standard of application software, quality improvement of total software, and reusability extension. Scope of our development includes core services of library automation system such as acquisition, list-up, loan-and-return, and their related services. We focus on interoperation compatibility between elementary sub-systems throughout complex network and structural features. Reanalyzing and standardizing each part of the system under the concept on the cloud of service, we construct an integrated development environment for generating, test, operation, and maintenance. Finally, performance analyses are performed about resource usability of server, memory amount used, and response time of server etc. As a result of measurements fulfilled over 5 times at different test points and using different data, the average response time is about 62.9 seconds for 100 clients, which takes about 0.629 seconds per client on the average. We can expect this result makes it possible to operate the system in real-time level proof. Resource usability and memory occupation are also good and moderate comparing to the conventional systems. As total verification tests, we present a simple proof to obey Electronic Cabinet Guidelines and a record of TTA authentication test for topics about SaaS maturity, performance, and application program features.

Funology Body : Classified Application System Based on Funology and Philosophy of the Human Body (Funology Body : Funology와 '몸의 철학' 이론을 바탕으로 한 어플리케이션 분류 검색 체계 연구)

  • Kihl, Tae-Suk;Jang, Ju-No;Ju, Hyun-Sun;Kwon, Ji-Eun
    • Science of Emotion and Sensibility
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    • v.13 no.4
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    • pp.635-646
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    • 2010
  • This article focuses on Funology and a new classified application system based on concept of language and thought which are formed by body experience. It is defined by Funology Body as that. Funology Body is classifying and searching system which are consisted of a body, world (environment), and device tool. The body is sectioned by Brain, Eyes, Ears, Nose, Mouth, Hand, Torso, Feet, and Heart according as parts of the human body. This allows intuiting and experience searching as making classified system connected to the application relationship with concept of an each part of body. The Brain of the body is sub-classified by Book, Account, Business, Memory, Education, Search, and Aphorism to imply the application with thought. The Eyes take Video, Photography, and Broadcast for visibility. The Ears is categorized as Music, Instrument, Audio, and Radio for hearing. The Nose gets Perfume, Smell for olfactory sense. The Mouth is sectioned by Food, SNS, Chatting, Email, and Blog for eating and communication. The Hand sorts into Games, Kits, and Editing to handle, create, and play. The Torso is grouped by Health, Medical, Dance, Sport, Fashion, and Testyuorself related by protecting internal and meaning of the body core. The Feet is classified by Travel, Transportation, Map, and Outdoor for moving and concept of expanding the terrain. The Heart is consisted of Fear, Anger, Joy, Sadness, Acceptance, Disgust, Expectation, and Surprise for a human feeling. Beyond that, the World takes News, Time, Weather, Map, Fortune, and Shop, and Device tool gets Interface, Utilities. The Funology Body has a unique characteristic of giving intuitive and sensuous pleasure and reflection of users' attitude and taste for changing application flexibly.

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Design of Low Power Optical Channel for DisplayPort Interface (저전력 광채널용 디스플레이포트 인터페이스 설계)

  • Seo, Jun-Hyup;Park, In-Hang;Jang, Hae-Jong;Bae, Gi-Yeol;Kang, Jin-Ku
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.11
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    • pp.58-63
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    • 2013
  • This paper presents a transceiver design for DisplayPort interface using an optical channel. By converting the electronic channel to the optical channel, the DisplayPort's main channel can provide a high-speed data transmission for long distance. The design converting the electronic channel to the optical channel in the main channel and AUX channel of the DisplayPort is presented in this paper. Futhermore, the HPD signal transmission by using AUX channel is proposed. In order to minimize power consumption, this paper also proposed a method of controlling the TX block in the main link. The proposed system is designed by a FPGA and an optical module. The FPGA used 651 ALUT(adaptive look-up table)s, 511 resisters and 324 block memory bits. The maximum operating rate of the FPGA is 250MHz. With the proposed power control scheme, 740mW of power dissipation reduction can be achieved at the main link optical TX module.

A Deep Learning-based Hand Gesture Recognition Robust to External Environments (외부 환경에 강인한 딥러닝 기반 손 제스처 인식)

  • Oh, Dong-Han;Lee, Byeong-Hee;Kim, Tae-Young
    • The Journal of Korean Institute of Next Generation Computing
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    • v.14 no.5
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    • pp.31-39
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    • 2018
  • Recently, there has been active studies to provide a user-friendly interface in a virtual reality environment by recognizing user hand gestures based on deep learning. However, most studies use separate sensors to obtain hand information or go through pre-process for efficient learning. It also fails to take into account changes in the external environment, such as changes in lighting or some of its hands being obscured. This paper proposes a hand gesture recognition method based on deep learning that is strong in external environments without the need for pre-process of RGB images obtained from general webcam. In this paper we improve the VGGNet and the GoogLeNet structures and compared the performance of each structure. The VGGNet and the GoogLeNet structures presented in this paper showed a recognition rate of 93.88% and 93.75%, respectively, based on data containing dim, partially obscured, or partially out-of-sight hand images. In terms of memory and speed, the GoogLeNet used about 3 times less memory than the VGGNet, and its processing speed was 10 times better. The results of this paper can be processed in real-time and used as a hand gesture interface in various areas such as games, education, and medical services in a virtual reality environment.

Effect of RTA Treatment on $LiNbO_3$ MFS Memory Capacitors

  • Park, Seok-Won;Park, Yu-Shin;Lim, Dong-Gun;Moon, Sang-Il;Kim, Sung-Hoon;Jang, Bum-Sik;Junsin Yi
    • The Korean Journal of Ceramics
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    • v.6 no.2
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    • pp.138-142
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    • 2000
  • Thin film $LiNbO_3$MFS (metal-ferroelectric-semiconductor) capacitor showed improved characteristics such as low interface trap density, low interaction with Si substrate, and large remanent polarization. This paper reports ferroelectric $LiNbO_3$thin films grown directly on p-type Si (100) substrates by 13.56 MHz RF magnetron sputtering system for FRAM (ferroelectric random access memory) applications. RTA (rapid thermal anneal) treatment was performed for as-deposited films in an oxygen atmosphere at $600^{\circ}C$ for 60sec. We learned from X-ray diffraction that the RTA treated films were changed from amorphous to poly-crystalline $LiNbO_3$which exhibited (012), (015), (022), and (023) plane. Low temperature film growth and post RTA treatments improved the leakage current of $LiNbO_3$films while keeping other properties almost as same as high substrate temperature grown samples. The leakage current density of $LiNbO_3$films decreased from $10^{-5}$ to $10^{-7}$A/$\textrm{cm}^2$ after RTA treatment. Breakdown electric field of the films exhibited higher than 500 kV/cm. C-V curves showed the clockwise hysteresis which represents ferroelectric switching characteristics. Calculated dielectric constant of thin film $LiNbO_3$illustrated as high as 27.9. From ferroelectric measurement, the remanent polarization and coercive field were achieved as 1.37 $\muC/\textrm{cm}^2$ and 170 kV/cm, respectively.

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Development of a Real-time Error-detection System;The Case study of an Electronic Jacquard

  • Huh, Jae-Yeong;Seo, Chang-Jun
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2588-2593
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    • 2003
  • Any system has the possibility of an error occurrence. Even if trivial errors were occurred, the original system would be fatally affected by the occurring errors. Accordingly, the error detection must be demanded. In this paper, we developed a real-time error detection system would be able to apply to an electronic Jacquard system. A Jacquard is a machine, which controls warps while weaving textiles, for manufacturing patterned cloth. There are two types of mechanical and electronic Jacquard. An electronic Jacquard is better than a mechanical Jacquard in view of the productivity and realizability for weaving various cloths. Recent weaving industry is growing up increasingly due to the electronic Jacquard. But, the problem of wrong weaving from error data exists in the electronic Jacquard. In this research, a real-time error detection system for an electronic Jacquard is developed for detecting errors in an electronic Jacquard in real-time. The real-time system is constructed using PC-based embedded system architecture. The system detects the occurring errors in real-time by storing 1344 data transferred in serial from an electronic Jacquard into memory, and then by comparing synchronously 1344 data stored into memory with 1344 data in a design file before the next data would be transferred to the Jacquard for weaving. The information of detected errors are monitored to the screen and stored into a file in real-time as the outputs of the system. In this research, we solve the problem of wrong weaving through checking the weaving data and detecting the occurred errors of an electronic Jacquard in real-time.

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Framework Implementation of Image-Based Indoor Localization System Using Parallel Distributed Computing (병렬 분산 처리를 이용한 영상 기반 실내 위치인식 시스템의 프레임워크 구현)

  • Kwon, Beom;Jeon, Donghyun;Kim, Jongyoo;Kim, Junghwan;Kim, Doyoung;Song, Hyewon;Lee, Sanghoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.11
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    • pp.1490-1501
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    • 2016
  • In this paper, we propose an image-based indoor localization system using parallel distributed computing. In order to reduce computation time for indoor localization, an scale invariant feature transform (SIFT) algorithm is performed in parallel by using Apache Spark. Toward this goal, we propose a novel image processing interface of Apache Spark. The experimental results show that the speed of the proposed system is about 3.6 times better than that of the conventional system.

Bi-directional Bus Architecture Suitable to Multitasking in MPEG System (MPEG 시스템용 다중 작업에 적합한 양방향 버스 구조)

  • Jun Chi-hoon;Yeon Gyu-sung;Hwang Tae-jin;Wee Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.4 s.334
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    • pp.9-18
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    • 2005
  • This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.

Development of Expert System For Designing Power Transmission Gears(I) -Diagnosis of the Causes and Remedies of Gear Failures- (동력전달용 치차설계 전문가 시스템 개발연구(I) -치차파손의 원인과 대책의 진단-)

  • 정태형;변준형;이규호
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.15 no.6
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    • pp.2026-2036
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    • 1991
  • An expert system is developed which can diagnose the causes and remedies of the failures of power transmission gears. The basic components of the expert system are knowledge base, inference engine, and working memory. The knowledges in knowledge base are classified into the knowledges for determining the failure types and for diagnosis of causes and remedies of the failures. The former is represented hierarchically into the main category of eleven groups by rules and the sub category of twenty four groups by facts, while the later is represented by facts according to the each group of knowledges. In the inference engine some considerations are implemented, i.e., the backward chaining method and depth first search to determine the category of the failures, the meta-knowledges to shorten the search space, the certainty factor to evaluate the reliability of result, and the unification strategy to diagnose the causes and remedies of the failures. The working memory is established to hold the results during inference temporarily. In addition, knowledge acquisition facility, explanation facility, and user interface are included for the usefulness of user. This expert system is written with the PROLOG programming language on IBM-PC compatible computer operated by MS-DOS and be executed alone.

A Realtime Hardware Design for Face Detection (얼굴인식을 위한 실시간 하드웨어 설계)

  • Suh, Ki-Bum;Cha, Sun-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.2
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    • pp.397-404
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    • 2013
  • This paper propose the hardware architecture of face detection hardware system using the AdaBoost algorithm. The proposed structure of face detection hardware system is possible to work in 30frame per second and in real time. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data by Matlab, and finally detected the face using this data. This paper describes the face detection hardware structure composed of image scaler, integral image extraction, face comparing, memory interface, data grouper and detected result display. The proposed circuit is so designed to process one point in one cycle that the prosed design can process full HD($1920{\times}1080$) image at 70MHz, which is approximate $2316087{\times}30$ cycle. Furthermore, This paper use the reducing the word length by Overflow to reduce memory size. and the proposed structure for face detection has been designed using Verilog HDL and modified in Mentor Graphics Modelsim. The proposed structure has been work on 45MHz operating frequency and use 74,757 LUT in FPGA Xilinx Virtex-5 XC5LX330.