• Title/Summary/Keyword: memory interface

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The study of propulsion control system (추진제어장치 특성 연구)

  • Kwon Il-Dong;Kim Dong-Myung;Chung Eun-Sung;Lee Sang-Jun;Choi Jong-Muk
    • Proceedings of the KSR Conference
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    • 2005.05a
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    • pp.291-298
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    • 2005
  • This paper describes the characteristic feather of propulsion system adopting mass production. The train formation is composed of 4 cars by 2 Motor cars and 2 Train cars. Acceleration rate must be 3.0 km/h/s or more when the car starts up to 35km/h by 16ton of passenger load. The system information supervision is easy because the system is controlled to perfect digital circuits, all information of an action is stored in a memory and is managed. The control system is composed of a fully digital circuit and a high level software such as C language. The DSP TMS320C31 is used for main processor and has the capability of 50MHz, 32bit floating point operation and has a C compiler. Therefore, the implementation of control algorithm and the change of function are easy. VVVF inverter using IGBT conducted variable combined test, environment test using chamber, interface test and field test etc.

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A VLSI implementation of image processor for facsimile and digital copier (팩시밀리 및 디지털 복사기를 위한 고속 영상 처리기의 VLSI구현)

  • 박창대;정영훈;김형수;김진수;권오준;홍기상;장동구;박기용;김윤수
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.1
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    • pp.105-113
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    • 1998
  • A new image processor is implemented for high-speed digital copiers and facsimiles. The imgage processor performs CCD and CIS interface, pre-processing, enlargement andreduction of gray level image, and various halftoning algorithms. Implemented halftoning algorithms are simple thresholding, fuzzy based mixed mode thresholding, dithering, and edge enhanced error diffusion. The result of binarization is transferred to a printer with serial or paralel output ports. Line by line pipelined data prodessing architecture is employed with time sharing access of the external memory. In receiving mode, it converts the resolution of received binary image for compatibility with conventional facsimile. In copy mode, a line of A3 paper with 400 dpi is processed with in 2.5 ms. The prototype of image processor was implemented usig Laser Programmable Gate Array (LPGA) with 0.8.mu.m technology.

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A SSN-Reduced 5Gb/s Parallel Transmitter

  • Lee, Seon-Kyoo;Kim, Young-Sang;Park, Hong-June;Sim, Jae-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.4
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    • pp.235-240
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    • 2007
  • A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.

An Implementation Device Driver and API for PC Card Cryptographic Token Using MPC860 (MPC860을 이용한 PC카드 보안토큰 장치구동기 및 API 설계/구현)

  • 김기홍;박종욱;윤장홍
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 2001.11a
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    • pp.297-301
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    • 2001
  • PC카드 형태로 개발되어 사용되는 보안토큰은 다양한 보안서비스를 바탕으로 차세대 정보보호 기술의 핵심기술로 떠오르고 있다. PC카드 보안토큰 휴대용 컴퓨터 운용을 위한 메모리 카드 표준 인터페이스를 수용하여 다양한 암호알고리즘 수행이 가능하고, 사용자의 요구조건을 비교적 쉽게 수용하고, 아울러 다양한 응용분야에 사용되는 등의 장점을 가지고 있다. 본 논문에서는 Motorola PowerPC 기반의 MPC860 마이크로 프로세서가 장착된 제어보드를 이용하여 PC카드 보안토큰에 대한 PCMCIA(Personal Computer Memory Card International Association) 카드 장치구동기 및 API(Application Program Interface)를 설계/구현하여 각각의 기능시험을 통해 그 기능들을 검증하였다.

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Efficiency Enhancement of CFDS Code (CFDS 코드의 효율성 개선)

  • Kim J. G.;Lee J.;Kim C.;Hong S. K.;Lee K. S.;Ahn C. S.
    • 한국전산유체공학회:학술대회논문집
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    • 2005.04a
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    • pp.123-127
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    • 2005
  • The numerical analyses of the complicated flows are widely attempted in these days. Because of the enormous demanding memory and calculation time, parallel processing is used for these problems. In order to obtain calculation efficiency, it is important to choose proper domain decomposition technique and numerical algorithm. In this research we enhanced the efficiency of the CFDS code developed by ADD, using parallel computation and newly developed numerical algorithms. For the huge amount of data transfer between blocks non-blocking method is used, and newly developed data transfer algorithm is used for non-aligned block interface. Recently developed RoeM scheme is adpoted as a spatial difference method, and AF-ADI and LU-SGS methods are used as a time integration method to enhance the convergence of the code. Analyses of the flows around the ONERA M6 wing and the high angle of attack missile configuration are performed to show the efficiency improvement.

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A study on the efficient system call interface supporting minimum memory copy (메모리 복사를 최소화 하는 효율적인 시스템 호출 인터페이스에 관한 연구)

  • Song, Chang-Yong;Kim, Eun-Gi
    • Proceedings of the Korea Information Processing Society Conference
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    • 2003.11b
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    • pp.1097-1100
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    • 2003
  • UNIX/LINUX 시스템에서 로컬 파일 시스템의 파일 데이터가 네트워크를 통해서 원격지 시스템에 전송되는 경우, 사용자와 커널(Kernel) 공간 사이에서의 메모리 복사가 적어도 2 회에 걸쳐 수행된다. 이러한 사용자와 리눅스(Linux) 커널 공간 사이에서 이루어지는 메모리 복사는 데이터 전송에 소요되는 시간을 증가시키고, 잦은 시스템 호출의 호출은 응용 프로세스와 리눅스 커널 간 문맥 교환(context switching)의 발생을 빈번하게 야기한다. 본 연구에서는 이러한 문제점들을 해결하기 위하여 필요한 경우 사용자와 리눅스 커널 사이에서의 메모리 복사를 수행하지 않고, 커널 공간 내에서의 메모리 복사를 최대한 제한할 수 있는 새로운 알고리즘을 제시한다.

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Digital Autopilot Implementation Using Microprocessor (마이크로프로세서을 이용한 디지털 자동조정장치의 실현)

  • 이명희;권오규
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.41 no.3
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    • pp.281-291
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    • 1992
  • This paper deals with the digital autopilot implementation for a launch vehicle. We propose a hardware and software system for digital autopilot implemented by microprocessor. The hardware system designed in this paper consists of CPU and memory board with 80286 MPU and 80287 NPU and I/O interface with A/D and D/A converters. The software system developed is composed of power-on self-test program, initializing program, interrupt service program, and control program. The performance of the overall system controlled by the digital autopilot implemented in this paper is evaluated via real-time simulations, which show that the control performances are satisfactory.

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Study of Event Recorder with Recording Voice Communication (음성 통화 저장 기능을 제공하는 고속전철용 Event Recorder 연구)

  • Song, Gyu-Youn;Lee, Sang-Nam;Ryu, Hee-Moon;Paik, Jin-Sung
    • Proceedings of the KSR Conference
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    • 2008.06a
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    • pp.1962-1967
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    • 2008
  • A event recorder system stores a train speed and the related information for train operation in real time. Using those information, we can analysis the train operation and the reason of train accident. Currently the event recorder only manipulate the data related the train operation mechanically and electrically. In this paper we propose the event recorder to record the voice communication between the manager in the control center and train operator. By recording the voice communication in the high speed train, the correctness of analysis of train accident can be increased. The system architecture of the event recorder with voice recording is studied and interface between other equipment is proposed. And the software architecture of new event recorder is developed. We study the method of converting analog voice signal into digital data and compressing method. Also the architecture of memory to store the compressed voice data and regeneration of original analog voice are studied.

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Recent Development of MRAM Technology

  • Miyazaki, T.;Ando, Y.;Kubota, H.
    • Journal of Magnetics
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    • v.8 no.1
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    • pp.36-44
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    • 2003
  • Three topics which are related to technologies for developing of large capacity MRAM over Gbits are reviewed. First, it is stressed that inelastic-electron-tunnel-tunneling spectroscopy(IETS) is a powerfull method to investigate the interface state between magnetic electrodes and insulator. Second, magnetic tunnel junctions with small bias voltage dependence are introduced. Finally, fabrication method of carbon masks for very small magnetic tunnel junctions is demonstrated. These three topics were presented at 47^{th} MMM 2002 conference and each paper will appear in the proceedings.

Architecture of Web-Based Real-Time Monitoring Systems (웹 기반 실시간 모니터링 시스템의 구조)

  • Park, Hong-Seong;Jeong, Myeong-Sun;Kim, Bong-Sun
    • Journal of Institute of Control, Robotics and Systems
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    • v.7 no.7
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    • pp.632-639
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    • 2001
  • This paper proposes an improved architecture of web-based monitoring systems for monitor of processes in plants from the soft real-time point of view. The suggested model is designed to be able to guarantee the temporal and spatial consistency and transmit the monitoring data periodically via the intranet and the Internet. The model generates one thread for monitoring management, one DB thread, one common memory, and corresponding monitoring threads to clients. The monitoring thread is executed during the smaller time than the execution time of the process used in the conventional methods such as CGI and servlet method. The Java API for the server API, VRML, EAI(External Authoring Interface) and Java Applets for efficient dimensional WEB monitoring are used. The proposed model is implemented and tested for a FMS plant, Some examples show that the proposed model is useful one.

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