• 한국철도학회:학술대회논문집
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• 한국철도학회 2010년도 춘계학술대회 논문집
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• pp.1068-1074
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• 2010

In high speed railway, event recorder is essential system for analyzing the cause of train accident. It stores train operation sent by train control system in safe memory unit. Crash protected memory, the safe memory unit for event recorder, keeps the stored contents from severe environment. For crash protected memory, we have designed the architecture of concrete enclosure and controller board. Proposed system provides large volume of memory capacity and fault tolerance architecture. For checking the characteristics of proposed crash protected memory specification, the simulation is executed. Simulation results shows the designed crash protected memory meets all requirements.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• 한국정밀공학회지
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• 제16권2호통권95호
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• pp.15-22
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• 1999

This paper demonstrates the feasibility of Shape Memory Alloy (SMA) actuators in controlling the motion of micro active catheter. The dynamic behavior of SMA is obtained by several experiments for the design of the controller. With the control parameters obtained in experiments, temperature feedback control algorithm is proposed and realized. The prototype of micro active catheter is fabricated, and its control performance which uses the designed controller is investigated. The results obtained show the potential of the SMA as viable means for actuating the micro active catheter.

• 대한기계학회논문집
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• 제19권1호
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• pp.263-270
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• 1995

The use of the shape memory alloy, Nitinol wire, is investigated as an actuator for enhancing the damping in structural vibration systems. The first-order mathematical model of the Nitinol wire is obtained from the experimental data for an actuator. Finite element method is utilized for the strain gage sensor model, which is installed at the root of cantilever beam. A simple system, cantilever beam, is built as a flexible structural system to implement a control law with the Nitinol wire actuator. The system model including sensor and actuator is derived, which agrees with the experimental results. The actuator dynamics is augmented with the system so as to design PI controller and the one of robust controllers, LQG/LTR controller, and the control laws are implemented experimentally. The experimental study shows the feasibility of utilizing the Nitinol wire as an actuator for the purpose of vibration control.

• ETRI Journal
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• 제32권1호
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• pp.84-92
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• 2010

This paper proposes the semaphore authority management (SAM) controller to optimize the dual-port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank enabling the exchange of data between two processors at high speed has been developed for mobile multimedia systems based on dual-processors. However, the latency of DPSDRAM caused by the semaphore for preventing the access contention at the shared bank slows down the data transfer rate and reduces the memory bandwidth. The methodology of SAM increases the data transfer rate by minimizing the semaphore latency. The SAM prevents the latency of reading the semaphore register of DPSDRAM, and reduces the latency of waiting for the authority of the shared bank to be changed. It also reduces the number of authority requests and the number of times authority changes. The experimental results using a 1 Gb DPSDRAM (OneDRAM) with the SAM controllers at 66 MHz show 1.6 times improvement of the data transfer rate between two processors compared with the traditional controller. In addition, the SAM shows bandwidth enhancement of up to 38% for port A and 31% for port B compared with the traditional controller.

• 한국정보통신학회논문지
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• 제15권3호
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• pp.521-527
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• 2011

군용 Single Board Computer(이하 SBC)에 주로 사용되는 중앙 처리 장치(Central Processing Unit)는 주로 Power PC의 계열이며 Freescale 사의 G4 계열인 74xx 프로세서가 주로 사용된다. 이러한 CPU인 7447A는 System Controller를 통하여 SBC 내의 주 기억 장치와 고속으로 데이터를 주고받는다. 본 논문에서는 위와 같은 SBC의 구조에서 System Controller와 DDR 메모리 소자 간 I/F를 구현함에 있어 PCB 적층 구조, 소자들의 Layout, 임피던스매칭과 Rugged 환경에서 적용 되는 동작 가능한 DDR 메모리를 모듈로 설계하여 구현하였다. 또한, 군용환경에 적용하기위한 SBC의 형상은 주로 6U, 3U의 표준 형태로 설계되어져야 한다. 메모리의 단종을 대비하여 메모리를 모듈화하고 System Controller와 모듈간의 최적의 전기적인 I/F매칭과 신호의 cross over를 고려한 Artwork반영, 존재하는 PCB의 제한조건을 고려해서 시뮬레이션과 설계 및 구현하는 방안을 제안한다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 추계종합학술대회
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• pp.768-771
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• 2007

낸드 플래시 메모리는 최근 많은 디지털 기기에서 사용되고 있으며 그 용량과 성능면에서의 발전이 급격이 이루어지고 있다. 낸드 플래시 메모리는 읽고 쓰기 회수에 제한이 있어 이 수명이 다하면 데이터의 신뢰성을 보장하기 어렵다. 이 때문에 낸드 플래시 데이터의 오류를 검출하는 ECC(Error Correction Code) 알고리즘의 적용이 필수적이다. 기존에는 ECC 알고리즘을 논리 게이트로 구현하였으나 본 논문에서는 룩업 테이블 방식을 사용하여 신뢰성과 데이터 처리 시간을 향상시키고자 한다.

• 대한전기학회논문지:전력기술부문A
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• 제52권11호
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• pp.647-654
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• 2003

As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).

• 한국정밀공학회지
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• 제12권9호
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• pp.167-174
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• 1995

This paper experimentally demonstrates the feasibility of using shape memory alloy(SMA) actuators in controlling structural vibrations of a flexible cantilevered beam. The dynamic characteristics of the SMA actuator are identified and integrated with the beam dynamics. Three types of control schemes; constant amplitude controller(CAC), proportional amplitude controller (PAC) and sliding mode controller(SMC) are designed. The CAC and PAC are determined on the basis of physical phenomenon of the SMA actuator, while teh SMC is formulated in a mathematical manner. The proposed controllers are implemented and evaluated at various operating condirions by investigating the control level of suppression in transient vibration.

• 대한임베디드공학회논문지
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• 제14권2호
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.