• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.540-543
• /
• 2010

POWER PC series are common to the Central Processing Unit for Military Single Board Computer. Among them, G4 group, which contains the 74xx series supported by Freescale manufacturer is mainly used in the Military applications. We focus on the Interface between memory and controller. PCB stacking method, component routing, impedance matching and harsh environment for Military spec are the main constraints for implementation. Also, we developed memory as a module for the consideration of Military environments. The overall type of SBC should be designed by the form of 6U VME or 3U VME.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.877-880
• /
• 2005

As DMB, 3D game, Internet and movie is serviced for the recent mobile devices, high resolution display devices beyond VGA become used. Implementation of real-time moving pictures of 30렌 by software programming is difficult because the performance of mobile processors is not so high. The full frame moving picture can be supported by using specific hardware. In this paper, an OLED controller that is consists of flash memory controller and OLED interface is proposed for real-time moving picture on mobile displays. The proposed OLED controller is implemented in FPGA and the performance is evaluated.

• 제어로봇시스템학회:학술대회논문집
• /
• 1990.10b
• /
• pp.1327-1331
• /
• 1990

A new dual loop controller using color LCD bar graphs with LED back lights has been developed. An optional memory card is used to load or save the controller configuration, which may be a preprogrammed standard package or a user-programmed configuration, in addition to the built-in functions ready for user selection. The bar-graph display is selectable for single-loop or dual-loop use. A high grade of self-tuning functions using a modeling technique is built-in as standard. The controller can accommodate optional plug-in modules for thermocouples, communication, etc. All the options are fully field upgradable.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.6
• /
• pp.808-816
• /
• 2016

As the number of CPU/GPU cores and IPs in SOC increases and applications require explosive memory bandwidth, simultaneously achieving good throughput and fairness in the memory system among interfering applications is very challenging. Recent works proposed priority-based thread scheduling and channel partitioning to improve throughput and fairness. However, combining these different approaches leads to performance and fairness degradation. In this paper, we analyze the problems incurred when combining priority-based scheduling and channel partitioning and propose dynamic priority thread scheduling and adaptive channel partitioning method. In addition, we propose dynamic address mapping to further optimize the proposed scheme. Combining proposed methods could enhance weighted speedup and fairness for memory intensive applications by 4.2% and 10.2% over TCM or by 19.7% and 19.9% over FR-FCFS on average whereas the proposed scheme requires space less than TCM by 8%.

• 제어로봇시스템학회:학술대회논문집
• /
• 1997.10a
• /
• pp.1569-1572
• /
• 1997

In this paper, we present an associative memory network (AMN) controller for dynamic robot control. The purpose of using AMN is to reduce the size of required memory in storing and recalling large of daa representing input relationship of nonlinear functions. With the capability AMN can be used to dynamic robot control, which has nonlinear properties inherently. The proposed AMN control scheme has advantages for the inverse dynamics learning no limitatiion of inpur range, and insensitive of payload change. Computer simulations show the effectiveness and feasibility of proposed scheme.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.1
• /
• pp.77-82
• /
• 2014

SD memory cards are widely used in portable digital devices, and most of them exploit NAND flash memory as their storage, so that they have a feature of storing users' important data safely with low costs. In case of using NAND flash memory as storage, however, there is no method to store users' data if memory capacity is insufficient when transferring a large volume of data. This paper proposes a virtual SD memory card system. It used a SD memory card device driver to process data requested from a host by exploiting external storage rather than by exploiting flash memory as a memory core for storing data to the SD memory card. For experiment, it used the FPGA-based SD card slave controller IP on the SMC controller with a S3C2450 ARM CPU to test.

• 제어로봇시스템학회:학술대회논문집
• /
• 1992.10a
• /
• pp.230-235
• /
• 1992

We propose a method of generating data to train a neural network controller. The data can be prepared directly by an iterative learning technique which repeatedly adjusts the control input to improve the tracking quality of the desired trajectory. Instead of storing control input data in memory as in iterative learning control, the neural network stores the mapping between the control input and the desired output. We apply this concept to the trajectory control of a two link robot manipulator with a feedforward neural network controller and a feedback linear controller. Simulation results show good generalization of the neural network controller.

• Proceedings of the IEEK Conference
• /
• 2001.06d
• /
• pp.105-108
• /
• 2001

This paper proposed an efficient memory scheduling method (E$^2$M$^2$) by which the real-time image compression using 2-dimensional discrete wavelet transform(2-D DWT) is possible in an FPGA chip. In this paper, we assumed that the 2-D DWT was performed as the Mallat-tree. After the memory mapping method was proved in software, the memory controller was designed for an commercial SDRAM IC.

• Proceedings of the IEEK Conference
• /
• 2004.08c
• /
• pp.486-490
• /
• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.136-139
• /
• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.