• Title/Summary/Keyword: memory controller

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The Implemention of RTD-l000A based on ARM Microcontroller (ARM 마이크로컨트롤러 기반 RTD-1000A의 구현)

  • Kim, Min-Ho;Hong, In-Sik
    • Journal of Internet Computing and Services
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    • v.9 no.6
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    • pp.117-125
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    • 2008
  • With increase of concern about the Ubiquitous application, the necessity of the computer system which is miniaturized is becoming larger. The ARM processor is showing a high share from embedded system market. In this paper, ideal method for RTD-1000 controller construction and development is described using ARM microcontroller. Existing RTD-1000 measures distance of disconnection or defect of sensing casket by measuring receiving reflected wave which was sent via copper wire inside the leaking sensing rod. Using this RTD-1000, leakage and breakage of water and oil pipe can be sensed and it reports damage results to the networks. But, existing RTD-1000 wastes hardware resources much and costs a great deal to installation. Also, it needs a cooling device because the heating problem, and has some problem of the secondary memory unit such as the hard disk. So, long tenn maintenance has some problems in the outside install place. In this paper, for the resolving the problem of RTD-1000, RTD-1000A embedded system based on ARM is proposed and simulated.

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Flash Operation Group Scheduling for Supporting QoS of SSD I/O Request Streams (SSD 입출력 요청 스트림들의 QoS 지원을 위한 플래시 연산 그룹 스케줄링)

  • Lee, Eungyu;Won, Sun;Lee, Joonwoo;Kim, Kanghee;Nam, Eyeehyun
    • Journal of KIISE
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    • v.42 no.12
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    • pp.1480-1485
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    • 2015
  • As SSDs are increasingly being used as high-performance storage or caches, attention is increasingly paid to the provision of SSDs with Quality-of-Service for I/O request streams of various applications in server systems. Since most SSDs are using the AHCI controller interface on a SATA bus, it is not possible to provide a differentiated service by distinguishing each I/O stream from others within the SSD. However, since a new SSD interface, the NVME controller interface on a PCI Express bus, has been proposed, it is now possible to recognize each I/O stream and schedule I/O requests within the SSD for differentiated services. This paper proposes Flash Operation Group Scheduling within NVME-based flash storage devices, and demonstrates through QEMU-based simulation that we can achieve a proportional bandwidth share for each I/O stream.

An Application of Blackboard Architecture to Grating Scheduling System (블랙보드 구조의 그레이팅 스케쥴링 시스템에의 적용)

  • Choi, Kyu-Sung;Koh, Jong-Young;Cho, Tae-Ho
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.1
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    • pp.12-19
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    • 2000
  • In the development of a production process scheduling system a collaboration method must be defined for the cooperation among submodules within the system. The blackboard architecture is exploited for solving the collaboration problem, which is one of the problem solving architecture that belongs to the distributed artificial intelligence. The dynamic states of the problem solving processes are presented in the hierarchically constructed shared working memory called as a blackboard. The communication for the collaboration is done through the blackboard. The problem solving steps are contained in the global controller, one of a component that consists the blackboard architecture, as knowledge. The global controller activates proper submodules based on the knowledge. By applying the blackboard architecture the collaboration problem among submodules in the grating production process scheduling system (GPSS) has been solved as well as the system became adaptable to the future modifications and expansions.

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Design of Digital Calibration Circuit of Silicon Pressure Sensors (실리콘 압력 센서의 디지털 보정 회로의 설계)

  • Kim, Kyu-Chull
    • Journal of IKEEE
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    • v.7 no.2 s.13
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    • pp.245-252
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    • 2003
  • We designed a silicon pressure sensor interface circuit with digital calibration capability. The interface circuit is composed of an analog section and a digital section. The analog section amplifies the weak signal from the sensor and the digital section handles the calibration function and communication function between the chip and outside microcontroller that controls the calibration. The digital section is composed of I2C serial interface, memory, trimming register and controller. The I2C serial interface is optimized to suit the need of on-chip silicon microsensor in terms of number of IO pins and silicon area. The major part of the design is to build a controller circuit that implements the optimized I2C protocol. The designed chip was fabricated through IDEC's MPW. We also made a test board and the test result showed that the chip performs the digital calibration function very well as expected.

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PRMS: Page Reallocation Method for SSDs (PRMS: SSDs에서의 Page 재배치 방법)

  • Lee, Dong-Hyun;Roh, Hong-Chan;Park, Sang-Hyun
    • The KIPS Transactions:PartD
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    • v.17D no.6
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    • pp.395-404
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    • 2010
  • Solid-State Disks (SSDs) have been currently considered as a promising candidate to replace hard disks, due to their significantly short access time, low power consumption, and shock resistance. SSDs, however, have drawbacks such that their write throughput and life span are decreased by random-writes, nearly regardless of SSDs controller designs. Previous studies have mostly focused on better designs of SSDs controller and reducing the number of write operations to SSDs. We suggest another method that reallocates data pages that tend to be simultaneously written to contiguous blocks. Our method gathers write operations during a period of time and generates write traces. After transforming each trace to a set of transactions, our method mines frequent itemsets from the transactions and reallocates the pages of the frequent itemsets. In addition, we introduce an algorithm that reallocates the pages of the frequent itemsets with moderate time complexity. Experiments using TPC-C workload demonstrated that our method successfully reduce 6% of total logical block access.

Real-Time Fault Detection in Discrete Manufacturing Systems Via LSTM Model based on PLC Digital Control Signals (PLC 디지털 제어 신호를 통한 LSTM기반의 이산 생산 공정의 실시간 고장 상태 감지)

  • Song, Yong-Uk;Baek, Sujeong
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.44 no.2
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    • pp.115-123
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    • 2021
  • A lot of sensor and control signals is generated by an industrial controller and related internet-of-things in discrete manufacturing system. The acquired signals are such records indicating whether several process operations have been correctly conducted or not in the system, therefore they are usually composed of binary numbers. For example, once a certain sensor turns on, the corresponding value is changed from 0 to 1, and it means the process is finished the previous operation and ready to conduct next operation. If an actuator starts to move, the corresponding value is changed from 0 to 1 and it indicates the corresponding operation is been conducting. Because traditional fault detection approaches are generally conducted with analog sensor signals and the signals show stationary during normal operation states, it is not simple to identify whether the manufacturing process works properly via conventional fault detection methods. However, digital control signals collected from a programmable logic controller continuously vary during normal process operation in order to show inherent sequence information which indicates the conducting operation tasks. Therefore, in this research, it is proposed to a recurrent neural network-based fault detection approach for considering sequential patterns in normal states of the manufacturing process. Using the constructed long short-term memory based fault detection, it is possible to predict the next control signals and detect faulty states by compared the predicted and real control signals in real-time. We validated and verified the proposed fault detection methods using digital control signals which are collected from a laser marking process, and the method provide good detection performance only using binary values.

RIDS: Random Forest-Based Intrusion Detection System for In-Vehicle Network (RIDS: 랜덤 포레스트 기반 차량 내 네트워크 칩입 탐지 시스템)

  • Daegi, Lee;Changseon, Han;Seongsoo, Lee
    • Journal of IKEEE
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    • v.26 no.4
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    • pp.614-621
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    • 2022
  • This paper proposes RIDS (Random Forest-Based Intrusion Detection), which is an intrusion detection system to detect hacking attack based on random forest. RIDS detects three typical attacks i.e. DoS (Denial of service) attack, fuzzing attack, and spoofing attack. It detects hacking attack based on four parameters, i.e. time interval between data frames, its deviation, Hamming distance between payloads, and its diviation. RIDS was designed in memory-centric architecture and node information is stored in memories. It was designed in scalable architecture where DoS attack, fuzzing attack, and spoofing attack can be all detected by adjusting number and depth of trees. Simulation results show that RIDS has 0.9835 accuracy and 0.9545 F1 score and it can detect three attack types effectively.

FPGA Implementation of Real-time 2-D Wavelet Image Compressor (실시간 2차원 웨이블릿 영상압축기의 FPGA 구현)

  • 서영호;김왕현;김종현;김동욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.7A
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    • pp.683-694
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    • 2002
  • In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9%) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

Design and Implementation of the Driving Habit Management System Using Brainwave Sensing for Safe Driving (안전 운전을 위한 뇌파 감지를 통한 운전 습관 관리시스템의 설계 및 구현)

  • Yoo, Seungeun;Kim, Wansoo;Ma, Sanggi;Lee, Sangjun
    • Journal of IKEEE
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    • v.18 no.3
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    • pp.368-375
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    • 2014
  • Brain computer interface(BCI) technology has been continuously developed due to the continuous development of interface technology and the promotion of brain wave research. In this paper, we propose a driving habit management system by adopting BCI to transportation. The proposed system consists of the electroencephalogram(EEG) measuring unit, the EEG analysis unit, the memory section for storing the state information of drivers, the speed controller unit and the alarming section for generating warnings. Our proposed system can reduce the drowsy driving, improve the driving habits of users and help to prevent traffic accidents.

Development of Data Logger System for Ocean Bottom Seimometer (해저면지진계 데이터 기록장치 개발 연구)

  • Hong, Sup;Kim, Hyung-Woo;Lee, Jong-Moo;Choi, Jong-Su
    • Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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    • 2003.10a
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    • pp.336-339
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    • 2003
  • A digital data logging system has been developed for the purpose of a compact offline Ocean Bottom Seismometer(OBS). The Digital Data Logger(DDL) consists of A/D system, Micom with storage memory and firmware managing data files. The A/D system acquires data of 16bit/4ch with sampling rate of 250Hz per channel. The Micom, a micro controller board with T33521 processor of 8051 class, was equipped with 8 flash memories of 128MB for data storage capacity of 1GB. The firmware stores the acquiring data in form of binary files. The DDL was designated to be compact and light and to consume low energy as possible. The DDL is to interface with PC through USB(Universal Serial Bus). The performance of the DDL has been validated through tests with respect to a 3-axis seismometer.

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