• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.216-220
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• 1987

A graphic display and operator console system is developed for monitoring the operation of power plant. It has multiprocessor structure using VME bus and common memory. The graphic monitoring system is applied to fault tolerant control system for enhancing reliability of boiler analog controller. As a result, it displays all the operating date as color graphic images with 14 pages. Moreover, it can transfer the operator commands to the other micro-processors through common memory.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.492-494
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• 1993

CMAC (Cerebeller Model Articulation Controller) is kind of Neural Networks that imitate the human cerebellum. For storage and retrieval of learned data, the input of CMAC is used as a key to determine the memory location. he learned information is distributively stored in physical memory. The learning of CMAC is very fast and converged well, therefore, it effects the application of Pattern Recognition. Through the our experiment of Pattern Recognition, we will prove that CMAC is very suitable for On-line real time processing and incremental learning of Neural Networks.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.05a
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• pp.349-354
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• 1996

SACOM(Simulation Analyser with Cognitive Operator Model) is being developed at Korea Atomic Energy Research Institute to simulate human operator's cognitive characteristics during the emergency situations of nuclear power plans. An operator model with error mechanisms has been developed and combined into SACOM to simulate human operator's cognitive information process based on the Rasmussen's decision ladder model. The operational logic for five different cognitive activities (Agents), operator's attentional control (Controller), short-term memory (Blackboard), and long-term memory (Knowledge Base) have been developed and implemented on blackboard architecture. A trial simulation with a scenario for emergency operation has been performed to verify the operational logic. It was found that the operator model with error mechanisms is suitable for the simulation of operator's cognitive behavior in emergency situation.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.8
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• pp.155-163
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• 1996

This paper presents vibration and position tracking control of a smart structure using shape memory alloy(SMA) actuators. A governing equation of motion of the proposed structure is obtained via Hamilton's princeple. The dynamic characteristics of the SMA actuator are experimentally identified and incorporated with the governing equation to furnish a control system model. Subsequently, a sliding mode controller which has inherent robustness to external disturbances is formulated on the basis of the sliding mode conplacement, and also for the position tracking control of desired trajectories with low-frequency sine and square waves.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.8
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• pp.816-823
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• 2008

This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.

• Journal of Digital Contents Society
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• v.18 no.7
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• pp.1451-1456
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• 2017

In this research we discuss an integrated actuator-control system for advanced control of a smart Shape Memory Alloy (SMA) actuator. Toward this goal, we designed and fabricated an actuator-control module combining two SMA actuating units with a single-chip microprocessor, two different sensing elements, and an actuator driver. In our proposed system, sensing elements include a 6-axis single-chip motion sensor for orientation measurement and a circuit for resistance measurement of SMA wires. We experimentally verified our proposed actuator-control system using actuator driving, sensor data readings, and communication tests.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.4
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• pp.103-109
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• 2015

This paper presents the development of a ROM writer for shmoo test of a flash memory integrated into the MCU(Micro Controller Unit). A shmoo test is a graphical display of the response of a component or system varying over a range of conditions and inputs. Often used to represent the results of the testing of complex electronic systems such as computers or integrated circuits such as DRAMs, ASICs or microprocessors. A shmoo test and data write time(32k) of the development ROM writer is 6.4 seconds, which was improved by about 20% compared to the rate of the currently used ROM writer.