• 제목/요약/키워드: memory controller

검색결과 346건 처리시간 0.03초

모바일 디바이스를 위한 소형 CNN 가속기의 마이크로코드 기반 컨트롤러 (Microcode based Controller for Compact CNN Accelerators Aimed at Mobile Devices)

  • 나용석;손현욱;김형원
    • 한국정보통신학회논문지
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    • 제26권3호
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    • pp.355-366
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    • 2022
  • 본 논문은 프로그램 가능한 구조를 사용하여 재구성이 가능하고 저 전력 초소형의 장점을 모두 제공하는 인공지능 가속기를 위한 마이크로코드 기반 뉴럴 네트워크 가속기 컨트롤러를 제안한다. 대상 가속기가 다양한 뉴럴 네트워크 모델을 지원하도록 마이크로코드 컴파일러를 통해 뉴럴 네트워크 모델을 마이크로코드로 변환하여 가속기의 메모리 접근과 모든 연산기를 제어할 수 있다. 200MHz의 System Clock을 기준으로 설계하였으며, YOLOv2-Tiny CNN model을 구동하도록 컨트롤러를 구현하였다. 객체 감지를 위한 VOC 2012 dataset 추론용 컨트롤러를 구현할 경우 137.9ms/image, mask 착용 여부 감지를 위한 mask detection dataset 추론용으로 구현할 경우 99.5ms/image의 detection speed를 달성하였다. 제안된 컨트롤러를 탑재한 가속기를 실리콘칩으로 구현할 때 게이트 카운트는 618,388이며, 이는 CPU core로서 RISC-V (U5-MC2)를 탑재할 경우 대비 약 65.5% 감소한 칩 면적을 제공한다.

A Study on the Built-In Self-Test for AC Parameter Testing of SDRAM using Image Graphic Controller

  • Park, Sang-Bong;Park, Nho-Kyung;Kim, Sang-Hun
    • The Journal of the Acoustical Society of Korea
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    • 제20권1E호
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    • pp.14-19
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    • 2001
  • We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

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A Low Power Multi-Function Digital Audio SoC

  • Lim, Chae-Duck;Lee, Kyo-Sik
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.399-402
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    • 2004
  • This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

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임베디드 SoC를 위한 Bus-splitting 기법 적용 ECC 보안 프로세서의 구현 (An Implementation of ECC(Elliptic Curve Cryptographic)Processor with Bus-splitting method for Embedded SoC(System on a Chip))

  • 최선준;장우영;김영철
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.651-654
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    • 2005
  • In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

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A Thin Film Transistor LCD Module with Novel OverDriving Timing Controller

  • Yu, Hong-Tien;Huang, Juin-Ying;Tseng, Wen-Tse;Wen, Harchson
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.1053-1056
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    • 2004
  • Chunghwa Picture Tubes, LTD. (CPT) has developed a Novel TFT-LCD Driving Techniquel. This new technique is developed in combination with other state-of-the-art image processing solutions such as image compression / decompression, motion detection, and noise reduction. By applying the Novel Driving Technique to the high resolution TFT-LCD, it was found that the response time can be effectively reduced with a lower overall system cost by smaller frame memory requirement, lower EMI by less memory band-width. Likewise, higher display quality can also be achieved in that the unexpected noises generated by over-drive can be eliminated. The Novel TFT-LCD Driving Technique has been successfully implemented to the 30 inch WXGA (1280${\times}$768) resolution TFT LCD commercial TV module. It was found that the quality of moving picture was better improved compared with that of the conventional fast response driving method.

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퇴적층에서의 가스 하이드레이트 생성 특성 (Formation characteristics of gas hydrate in sediments)

  • 이재형;이원석;김세준;김현태;허대기
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2005년도 춘계학술대회
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    • pp.630-633
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    • 2005
  • Some gases can be formed into hydrate by physical combination with water under appropriate temperature and pressure condition. Besides them, it was found that the pore size of the sediments can affect the formation and dissociation of hydrate. In this study, formation temperatures of carbon dioxide and methane hydrate have been measured using isobaric method to investigate the effects of flow rates of gases on formation condition of hydrate in porous rock samples. The flow rates of gases were controlled using a mass flow controller. To minimize Memory effect, system temperature increased for the dissociation of gas hydrates and re-established the initial saturation. The results show that the formation temperature of hydrate decreases with increasing the injection flow rate of gas. This indicates that the velocity of gas in porous media may act as kinds of inhibitor for the formation of hydrate.

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광디스크 메모리에 있어서 Jitter 저감을 위한 신호계 조절효과 (A Study on Signal Control Effect for Lower Jitter Value in Optical Disc Memory)

  • 임실묵;허창우
    • 한국정보통신학회논문지
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    • 제5권7호
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    • pp.1295-1300
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    • 2001
  • 본 논문에서는 광디스크 메모리의 재생성능에 주요한 영향을 미치는 jitter를 향상시키는 방법이 검토되었다. 광디스크 제조공정에 있어서 타공정의 변수를 고정한 상태에서 단일의 조작을 통해 jitter value를 저감화시키기 위해 펄스 폭 조정기를 제작하였다. 펄스 폭 조정기폭 적용하여 입력신호의 level을 조정한 결과 6.9%의 최소 jitter value를 확보하였다.

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SMA 작동기를 이용한 HDD의 비접촉 시동 및 정지 기구의 실험적 성능 고찰 (Experimental Evaluation of HDD's Non-Contact Start/Stop Motion Using Shape Memory Alloy Actuator)

  • 임수철;박종성;최승복;박영필
    • 한국소음진동공학회:학술대회논문집
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    • 한국소음진동공학회 2001년도 춘계학술대회논문집
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    • pp.1122-1129
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    • 2001
  • In this work, we propose a new type of HDD suspension featuring shape memory ally (SMA) actuator in order to prevent the contact between the slider and disk. The principal design parameters are obtained from the modal analysis using finite element analysis, and then the dynamic model is established to formulate the control scheme for Non-Contact Start/Stop mode drive. Subsequently, a robust Η$_{\infty}$, control algorithm is designed by integrating experimentally-obtained SMA actuator dynamics to the proposed suspension system. The controller is empirically realized and control results for different load/unload profiles are presented in time domain. In addition, the contact signal between the slider and disk is measured by the electrical resistance method.istance method.

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멀티링 설계규칙검사를 위한 효과적인 하드웨어 가속기 (MultiRing An Efficient Hardware Accelerator for Design Rule Checking)

  • 노길수;경종민
    • 대한전자공학회논문지
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    • 제24권6호
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    • pp.1040-1048
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    • 1987
  • We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

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자동차 실내소음의 능동제어를 위한 고속 이산 신호처리 장치 개발 (Development of High Speed Digital Signal Processing Unit for Active Control of Noise Fields in Passenger Car)

  • 김인수;이강모;허현무;홍석윤
    • 소음진동
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    • 제6권2호
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    • pp.205-214
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    • 1996
  • Active noise control(ANC) requires the full capability of a modern digital signal processing module. This paper describes the digital signal processing unit which is designed for ANC of noise fields in passenger car. System hardware is designed to allow software controlled versatility as well as fully qutomatic operation. The developed system is provided with the ability to be self-operated except the case of upload/download of data and program between the personal computer and the system memory. Experimental results are presented to demonstrate ANC performance of noise fields in lightly damped enclosure and passenger car.

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