• Title/Summary/Keyword: memory accuracy

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Supervised learning-based DDoS attacks detection: Tuning hyperparameters

  • Kim, Meejoung
    • ETRI Journal
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    • v.41 no.5
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    • pp.560-573
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    • 2019
  • Two supervised learning algorithms, a basic neural network and a long short-term memory recurrent neural network, are applied to traffic including DDoS attacks. The joint effects of preprocessing methods and hyperparameters for machine learning on performance are investigated. Values representing attack characteristics are extracted from datasets and preprocessed by two methods. Binary classification and two optimizers are used. Some hyperparameters are obtained exhaustively for fast and accurate detection, while others are fixed with constants to account for performance and data characteristics. An experiment is performed via TensorFlow on three traffic datasets. Three scenarios are considered to investigate the effects of learning former traffic on sequential traffic analysis and the effects of learning one dataset on application to another dataset, and determine whether the algorithms can be used for recent attack traffic. Experimental results show that the used preprocessing methods, neural network architectures and hyperparameters, and the optimizers are appropriate for DDoS attack detection. The obtained results provide a criterion for the detection accuracy of attacks.

Comparative Analysis of PM10 Prediction Performance between Neural Network Models

  • Jung, Yong-Jin;Oh, Chang-Heon
    • Journal of information and communication convergence engineering
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    • v.19 no.4
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    • pp.241-247
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    • 2021
  • Particulate matter has emerged as a serious global problem, necessitating highly reliable information on the matter. Therefore, various algorithms have been used in studies to predict particulate matter. In this study, we compared the prediction performance of neural network models that have been actively studied for particulate matter prediction. Among the neural network algorithms, a deep neural network (DNN), a recurrent neural network, and long short-term memory were used to design the optimal prediction model using a hyper-parameter search. In the comparative analysis of the prediction performance of each model, the DNN model showed a lower root mean square error (RMSE) than the other algorithms in the performance comparison using the RMSE and the level of accuracy as metrics for evaluation. The stability of the recurrent neural network was slightly lower than that of the other algorithms, although the accuracy was higher.

A Memory-Efficient Fingerprint Verification Algorithm Using a Multi-Resolution Accumulator Array

  • Pan, Sung-Bum;Gil, Youn-Hee;Moon, Dae-Sung;Chung, Yong-Wha;Park, Chee-Hang
    • ETRI Journal
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    • v.25 no.3
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    • pp.179-186
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    • 2003
  • Using biometrics to verify a person's identity has several advantages over the present practices of personal identification numbers (PINs) and passwords. At the same time, improvements in VLSI technology have recently led to the introduction of smart cards with 32-bit RISC processors. To gain maximum security in verification systems using biometrics, verification as well as storage of the biometric pattern must be done in the smart card. However, because of the limited resources (processing power and memory space) of the smart card, integrating biometrics into it is still an open challenge. In this paper, we propose a fingerprint verification algorithm using a multi-resolution accumulator array that can be executed in restricted environments such as the smart card. We first evaluate both the number of instructions executed and the memory requirement for each step of a typical fingerprint verification algorithm. We then develop a memory-efficient algorithm for the most memory-consuming step (alignment) using a multi-resolution accumulator array. Our experimental results show that the proposed algorithm can reduce the required memory space by a factor of 40 and can be executed in real time in resource-constrained environments without significantly degrading accuracy.

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Bad Data Detection Method in Power System State Estimation (전력계통 상태 추정에서의 불량정보 검출기법)

  • Choi, Sang-Bong;Moon, Young-Hyun
    • Proceedings of the KIEE Conference
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    • 1990.11a
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    • pp.239-243
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    • 1990
  • This paper presents a algorithm to improve accuracy and reliability in state estimation of contaminated bad data. The conventional algorithms for detection of bad data confront the problems of excessive memory requirements and long computation time. In order to overcome measurement compensation approach is proposed to reduce computation time and partitioned measurement error model has the advantage of remarkable reduction in computation time and memory requirements in estimated error computation. The proposed algorithm has been tested for IEEE sample systems, which shows its applicability to on-line power systems.

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A study on the implementation of a tunable laser system for holebuning optical memory (Holeburning 광메모리용 가변파장 레이저 시스템의 구현에 관한연구)

  • 김민지
    • Proceedings of the Optical Society of Korea Conference
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    • 1998.08a
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    • pp.170-171
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    • 1998
  • Here are proposed the tunable laser for optical memory which uses the acousto-optic deflector. This laser includes the acousto-optic deflector in the Littrow mount configuration so that we may control the beam deflection by means of the induced RF. Consequently, we can achieve the higher speed and accuracy to compare with the Littrow monut configuration only.

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Bad Data Detection Method in Power System State Estimation (전력계통 상태주정에서의 불량정보 검출기법)

  • 최상봉;문영현
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.40 no.2
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    • pp.144-153
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    • 1991
  • This paper presents an algorithm to improve accuracy and reliability in the state estimation of contaminated bad data. The conventional algorithms for detection of bad data have the problems of excessive memory requirements and long computation time. In order to overcome these problems, a measurement compensation approach is proposed to reduce computation time, and the partitioned measurement error model has the advantage of remarkable reduction in computation time and memory requirements in estimated error computation. The proposed algorithm has been tested for IEEE sample systems, which shows its applicability to on-line power systems.

Survival Processing Advantage and Sex Differences in Location Memory (위치 기억에서의 생존 처리 이득과 성차)

  • Choi, Joon-Hyuk;Kim, Min-Shik
    • Korean Journal of Cognitive Science
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    • v.21 no.4
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    • pp.697-723
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    • 2010
  • Recent studies report that in terms of object memory, survival context has mnemonic advantage over other context conditions (e.g., Nairne et al, 2007). The present experiments explored whether this effect can also affect task-irreverent object location memory, and tested whether the context can change gender difference in object location memory. Participants were asked to rate the relevance of pictures presented at random locations (experiment 1) or words (experiment 2) under survival context or moving context. After rating the pictures or words, they answered recall test and location retrieval test. The results revealed higher accuracy in memory for objects encoded under survival context. Moreover, survival processing enhanced location memory, and the survival advantage in location memory emerged among woman.

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A Short-Term Prediction Method of the IGS RTS Clock Correction by using LSTM Network

  • Kim, Mingyu;Kim, Jeongrae
    • Journal of Positioning, Navigation, and Timing
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    • v.8 no.4
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    • pp.209-214
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    • 2019
  • Precise point positioning (PPP) requires precise orbit and clock products. International GNSS service (IGS) real-time service (RTS) data can be used in real-time for PPP, but it may not be possible to receive these corrections for a short time due to internet or hardware failure. In addition, the time required for IGS to combine RTS data from each analysis center results in a delay of about 30 seconds for the RTS data. Short-term orbit prediction can be possible because it includes the rate of correction, but the clock correction only provides bias. Thus, a short-term prediction model is needed to preidict RTS clock corrections. In this paper, we used a long short-term memory (LSTM) network to predict RTS clock correction for three minutes. The prediction accuracy of the LSTM was compared with that of the polynomial model. After applying the predicted clock corrections to the broadcast ephemeris, we performed PPP and analyzed the positioning accuracy. The LSTM network predicted the clock correction within 2 cm error, and the PPP accuracy is almost the same as received RTS data.

A 95% accurate EEG-connectome Processor for a Mental Health Monitoring System

  • Kim, Hyunki;Song, Kiseok;Roh, Taehwan;Yoo, Hoi-Jun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.436-442
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    • 2016
  • An electroencephalogram (EEG)-connectome processor to monitor and diagnose mental health is proposed. From 19-channel EEG signals, the proposed processor determines whether the mental state is healthy or unhealthy by extracting significant features from EEG signals and classifying them. Connectome approach is adopted for the best diagnosis accuracy, and synchronization likelihood (SL) is chosen as the connectome feature. Before computing SL, reconstruction optimizer (ReOpt) block compensates some parameters, resulting in improved accuracy. During SL calculation, a sparse matrix inscription (SMI) scheme is proposed to reduce the memory size to 1/24. From the calculated SL information, a small world feature extractor (SWFE) reduces the memory size to 1/29. Finally, using SLs or small word features, radial basis function (RBF) kernel-based support vector machine (SVM) diagnoses user's mental health condition. For RBF kernels, look-up-tables (LUTs) are used to replace the floating-point operations, decreasing the required operation by 54%. Consequently, The EEG-connectome processor improves the diagnosis accuracy from 89% to 95% in Alzheimer's disease case. The proposed processor occupies $3.8mm^2$ and consumes 1.71 mW with $0.18{\mu}m$ CMOS technology.

Analysis of the Stepped-Impedance Low Pass Filter using Sub-Gridding Finite-Difference Time-Domain Method (서브 그리딩 유한 차분 시간 영역법을 이용한 계단형 임피던스 저역 통과 필터 해석)

  • 노범석;최재훈;이상선;정제명
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.2
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    • pp.217-224
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    • 2002
  • One of the dominant aspects governing the accuracy of the FDTD method is the size of the spatial increment used in the model. The effect of having reduced cell size is to increase the computational time and memory requirements. To overcome these problems, sub-gridding technique can be used. This implies that the application of a sub-grid cell would provide improved accuracy without increasing the run time and computer resources considerably. In this paper, we describe the three dimensional sub-gridding technique that is applied to model only the fine structure region of interest. The detailed solution procedure is described and some test geometries were solved by both uniform grid and sub-grid models to validate the suggested approach. While keeping the accuracy, the computational time becomes 6 times faster and the memory requirement is reduced by a factor of 2.5 comparing to the conventional FDTD approach.