• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.21-24
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• 2000

Ferroelectric YMnO$_3$ thin films are excellent dielectric materials for high integrated ferroelectric random access memory (FRAM) with metal-ferroelectric-silicon field effect transistor (MFSFET) structure. In this study, YMnO$_3$ thin films were etched with C1$_2$/Ar gas chemistries in inductively coupled plasma (ICP). The maximum etch rate of YMnO$_3$ thin films is 285 $\AA$/min under C1$_2$/Ar of 10/0, 600 W/-200 V and 15 mTorr. The selectivities of YMnO$_3$ over CeO$_2$ and $Y_2$O$_3$ are 2.85, 1.72, respectively. The results of x-ray photoelectron spectroscopy (XPS) reflect that Y is removed dominantly by chemical reaction between Y and Cl, while Mn is removed more effective by Ar ion bombardment than chemical reaction. The results of secondary ion mass spectrometer (SIMS) were equal to these of XPS. The etch profile of the etched YMnO$_3$ film is approximately 65$^{\circ}$and free of residues at the sidewall.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.7
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• pp.68-80
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• 2002

An approach for composing a performance optimized computational code is suggested for latest microprocessors. The concept of the code optimization, called here as localization, is maximizing the utilization of the second level cache that is common to all the latest computer system, and minimizing the access to system main memory. In this study, the localized optimization of LU-SGS (Lower-Upper Symmetric Gauss-Seidel) code for the solution of fluid dynamic equations was carried out in three different levels and tested for several different microprocessor architectures most widely used in these days. The test results of localized optimization showed a remarkable performance gain up to 7.35 times faster solution, depending on the system, than the baseline algorithm for producing exactly the same solution on the same computer system.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.12
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• pp.685-697
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• 2001

Cache memories are small fast memories used to temporarily hold the contents of main memory that are likely to be referenced by processors so as to reduce instruction and data access time. In this paper, we represent analytical models of instruction fetch process for four types of instruction cache structures that can be used for superscalar processors. In the models, we define various kinds of architectural parameters and take cache miss and branch misprediction into consideration. To prove the correctness of the proposed models, we performed extensive simulations and compared the results with the analytical models. Simulation results showed that the proposed model can estimate the instruction fetch rate accurately within 10% error in most cases. Both analytical model and simulation show that the increase of cache misses reduces the instruction fetch rate more severely than that of branch misprediction does. However, the analytical model can explain the causes of performance degradation which cannot be uncovered by the simulation method only. The model is also able to provide exact relationship between cache miss and branch misprediction for instruction fetch analysis.

• Journal of KIISE:Databases
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• v.28 no.3
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• pp.334-343
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• 2001

Most of currently used videos have variable bit rate(VBR) characteristics. Since the display rate of VBR videos compared to CBR videos vary with time, it is not proper to configure resources of the VBR video server using the method proposed for the CBR video server. In this paper we propose an optimal resource configuration method for the VBR video server which is based on the probability model. The proposed method decides the amount of disk and memory, and the disk access cycle of the video server with the lowest hardware cost, while preserving the throughput of the video server. In addition, we show the usefulness of the method through the various experiments.

• Journal of Korea Society of Industrial Information Systems
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• v.15 no.2
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• pp.31-39
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• 2010

VoD(Video-on-Demand) servers have to provide timely processing guarantees for continuous media and reduce the storage and bandwidth requirements for continuous media. The compression techniques make the bit rates of compressed video data significantly variable from frame to frame. A VoD system should be able to provide the client with interactive operations such as fast forward and fast rewind in addition to normal playback of movie. However, interactive operations require additional resources such as storage space, disk bandwidth, memory and network bandwidth. In a stored video application such as VoD system, it is possible that a priori disk access patterns can be used to reserve the system resources in advance. In addition, clients of VoD server spend most of their time in playback mode and the period of time spent in interactive mode is relatively small. In this paper, I present the new buffer management scheme that provides efficient support for interactive operations in a VoD server using variable bit rate continuous media. Simulation results show that our strategy achieves 34% increase of the number of accepted clients over the LRU strategy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.236-236
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• 2008

(Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.341-350
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• 2003

In this paper, we evaluate the performance of a moving average (MA) channel estimation filter when space-time block coding transmit diversity (STBC-TD) is applied to the wideband direct sequence code division multiple access (WCDMA) forward link. And we present the infinite impulse response (IIR) filter scheme that can reduce the required memory buffer and the channel estimation delay time. This paper also compares the performance between MA filter scheme and IIR filter scheme in various Rayleigh fading channel environments through the bit error rate (BER) and the frame error rate (FER). Extensive computer simulation results show that transmission with STBC-TD provides a significant gain in performance over no transmit diversity technique, particularly at pedestrian speeds. If STBC-TD technique is employed in the channel estimator based on MA filter, it provides considerable performance gains against Rayleigh fading and reduces the optimum filter tap number. Consequently, the channel estimation delay time and the complexity of the receiver are reduced. In addition, the channel estimator based on IIR filter has the advantages such as little memory requirement and no delay time compared to the MA scheme. However, IIR filter coefficients is very sensitive to the mobile speed change and it exerts a serious influence upon the performance. For that reason, it is important to set uP the optimum IIR filter coefficients.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.1
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• pp.1-10
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• 2002

A space-time concatenated convolutional and differential coding scheme is employed in a multiuser direct-sequence code-division multiple-access(DS-CDMA) system. The system consists of single-user detectors (SUD), which are used to suppress multiple-access interference(MAI) with no requirement of other users' spreading codes, timing, or phase information. The space-time differential code, treated as a convolutional code of code rate 1 and memory 1, does not sacrifice the coding efficiency and has the least number of states. In addition, it brings a diversity gain through the space-time processing with a simple decoding process. The iterative process exchanges information between the differential decoder and the convolutional decoder. Numerical results show that this space-time concatenated coding scheme provides better performance and more flexibility than conventional convolutional codes in DS-CDMA systems, even in the sense of similar complexity Further study shows that the performance of this coding scheme applying to DS-CDMA systems with SUDs improves by increasing the processing gain or the number of taps of the interference suppression filter, and degrades for higher near-far interfering power or additional near-far interfering users.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.12
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• pp.1174-1180
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• 2011

Field Programmable Gate Array(FPGA)s are replacing traditional integrated circuits for space applications due to their lower development cost as well as reconfigurability. However, they are very sensitive to single event upset (SEU) caused by space radiation environment. In order to mitigate the SEU, on-board computer of STSAT-3 employed a triple modular redundancy(TMR) and scrubbing scheme. Experimental results showed that upset threshold energy was improved from 10.6 MeV to 20.3 MeV when the TMR and the scrubbing were applied to the on-board computer. Combining the experimental results with the orbit simulation results, calculated bit-flip rate of on-board computer is 1.23 bit-flips/day assuming in the worst case of STSAT-3 orbit.

• ETRI Journal
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• v.25 no.5
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• pp.337-344
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• 2003

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.