• Journal of the Korea Society of Computer and Information
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• v.22 no.12
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• pp.9-15
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• 2017

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.15-18
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• 2003

Flash memory becomes more important for its fast access speed, low-power, shock resistance and nonvolatile storage. But its native restrictions that have limited 1ifetime, inability of update in place, different size unit of read/write and erase operations need to managed by FTL(Flash Translation Layer). FTL has to control the wear-leveling, address mapping, bad block management of flash memory. In this paper, we focuses on the fast access to address mapping table and proposed the way of faster valid page search in the flash memory using the VPLT(Valid Page Lookup Table). This method is expected to decrease the frequency of access of flash memory that have an significant effect on performance of read and block-transfer operations. For the validations, we implemented the FTL based on Windows CE platform and obtained an improved result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.11
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• pp.967-969
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• 2013

In this paper, we propose an efficient mult-signature scheme based on a bilinear mapping for shared data in the cloud and prove the security of the proposed scheme using the difficulty of the computational Diffie-Hellman problem. For verification, the scheme is using the sum of the hash values of stored data rather than the entire data, which makes it feasible to reduce the size of the downloaded data.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.3
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• pp.134-138
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• 2009

We present a flash memory system with low cost and high performance for solid-state disk. The proposed flash system is constructed as a SLC with hot blocks and a MLC with cold blocks. Either the SLC or the MLC is selectively accessed on the basis of a position bit in a mapping table. Our results show that the system enables the SLC size to be reduced by about 80% relative to a conventional SLC while maintaining similar performance. And also, our system can improve a performance by above 60% comparing with a conventional MLC.

• Proceedings of the Korean Geotechical Society Conference
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• 2002.03a
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• pp.253-260
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• 2002

Chemical weathering processes related with mineralogical characters and ground water condition are very essential engineering problems in soluble rock masses. Detailed geological mapping were performed and 8 samples were collected from the 2 formations including various rock faces to deduce the possibility of the limestone cavity formation and their mechanism. Petrological descriptions and various petro-mineralogical experiments such as XRD analysis, clay mineral analysis, absorptivity test, impurity analysis were conducted to evaluate the cavity making processes. Laboratory solubility test for rock specimen were also carried out under the strong acid (pH=1) condition. From the experimental data and geological mapping data, it is found that the formation of limestone cavities in limestones are strongly related with geological structures such as beddings, cleavages and the contents of impurities rather than CaCO$_3$contents. In case of dolomites, rock textures, grain size, amounts and types of clay minerals as well as geological structures are major controlling factors of cavity forming processes

• Korean Journal of Remote Sensing
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• v.20 no.3
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• pp.207-214
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• 2004

This study focused on providing a methodology to utilize temporal information obtained from remotely sensed data for monitoring a wide variety of targets on the earth's surface. Generally, a methodology in understanding of global changes is composed of mapping, quantifying, and monitoring changes in the physical characteristics of land cover. The selected processing and analysis technique affects the quality of the obtained information. In this research, feature extraction methodology is proposed based on segmentation. It requires a series of processing of multitempotal images: preprocessing of geometric and radiometric correction, image subtraction/thresholding technique, and segmentation/thresholding. It results in the mapping of the change-detected areas. Here, the appropriate methods are studied for each step and especially, in segmentation process, a method to delineate the exact boundaries of features is investigated in multiresolution framework to reduce computational complexity for multitemporal images of large size.

• The Journal of Economics, Marketing and Management
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• v.5 no.1
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• pp.38-43
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• 2017

Purpose - The paper aims to study competency mapping in the organization and how does HR department focuses to provide a definitive road map to understand, design and implement competency models in the organization. Research Design, Data and Methodology - Descriptive research design has been used in the study. The sample size of the study is 75 consisting of employees working at DMRC, barakhamba road. A structured questionnaire was designed to collect the primary data. SPSS has been used to analyze the responses of the questionnaires. Results- DMRC frequently employs some form of competency mapping to understand how to most effectively employ the competencies of strengths of workers. Conclusion - To conclude, it was found that the company has cost effective system to recruit and select people which is working satisfactorily.

• Membrane and Water Treatment
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• v.2 no.4
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• pp.251-266
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• 2011

This work deals with the use of High Resolution Scanning Electron Microscopy (HRSEM) to verify ultrafiltration membrane selectivity at the end of the production line as well as membrane ageing. The first part of this work is focused on new membranes. It is shown that it is better to use sputtering metallization than vacuum deposition, as this latter technique entails thermal damage to the skin layer. Moreover, the impact of the metallization layer on the determination of the membrane pore size is studied and it is observed that no impact of the metallization step can be clearly defined for a metallization layer ranging from 3 to 12 nm. For example, an average pore size of 16.9 nm and a recovery rate of 6.5 % are observed for a 150 kDa cellulose acetate membrane. These results are in agreement with those given by the manufacturer: pore size ranging from 10 to 15 nm and recovery rate ranging from 5 to 10 %. The second part of this work focuses on the study of membrane ageing. A PVDF hollow fibre membrane is studied. It is shown that a 65 % decrease in the permeate flux can be linked to a decrease in the number of pores at the surface of the membrane and a decrease in the recovery rate. In conclusion, a mapping of the pores is performed for several new hollow fibre membranes used to produce drinking water, made of different materials, with different geometries and molecular weight cut-off. These results provide reference data that will help better understand the phenomena of membrane fouling and membrane ageing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.936-944
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• 2003

In this paper, we propose an AND/XOR-based technology mapping method for field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem to decompose a given Boolean circuit. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as error detecting/correcting, data encryption/decryption, and arithmetic circuits, efficiently. We conduct experiments using MCNC benchmark circuits. When using the proposed approach, the number of CLBs (configurable logic blocks) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), total equivalent gate counts are reduced by 65.5 %, maximum combinational path delay is reduced by 56.7 %, and maximum net delay is reduced by 80.5 % compared to conventional methods.

• Journal of IKEEE
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• v.22 no.1
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• pp.68-73
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• 2018

In this paper, we propose an efficient algorithm for mapping a $360^{\circ}$ circular image to a planar image. The proposed algorithm consists of obtaining size of the planar image, calculating the distance between the camera and the planar image, calculating horizontal angle of camera and planar image, calculating vertical angle between camera and planar image, calculating the position of a pixel that matches pixels in a $360^{\circ}$ circular image to pixels in a planar image. Experiments were performed to evaluate the efficient algorithm for mapping the proposed $360^{\circ}$ circular image to the plane image. The reconstruction rate of the mapped plane image was confirmed 99% and the image quality of the mapped plane image was confirmed 72%. Since the results were higher than the standard values of commercial software, the effectiveness of the algorithm was confirmed.