• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.143-152
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• 2012

In this paper hardware implementation of GF($2^{191}$) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF($2^m$), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.9
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• pp.1257-1263
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• 2018

Secure authentication technology is a fundamental building block for secure services for Internet of Things devices. Particularly, the multiplication operation is a core operation of public key cryptography, such as RSA, ECC, and SIDH. However, modern low-power processor, namely ARM Cortex-M3 processor, is not secure enough for practical usages, since it executes the multiplication operation in variable-time depending on the input length. When the execution is performed in variable-time, the attacker can extract the password from the measured timing. In order to resolve this issue, recent work presented constant-time solution for multiplication operation. However, the implementation still missed various speed-optimization techniques. In this paper, we analyze previous multiplication methods over ARM Cortex-M3 and provide optimized implementations to accelerate the speed-performance further. The proposed method successfully accelerates the execution-time by up-to 25.7% than previous works.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1074-1076
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• 2010

최근 스마트폰이 크게 활성화됨에 따라 스마트폰에서 이용할 수 있는 인터넷전화가 급부상하고 있다. 그러나 인터넷전화는 인터넷망을 이용하기 때문에 요금이 저렴한 반면에 보안이 취약한 문제점을 가지고 있다. 이에 따라 본 논문에서는 도청방지를 위해 모바일 인터넷전화 시스템에 적합한 암호 알고리즘인 RSA, ECC 등을 비교 분석한다. 향후 모바일 인터넷전화 시스템 개발시 암호 알고리즘을 적용하는데 참고할 수 있다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.587-592
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• 2010

We have fabricated schottky barrier diode (SBDs) using polar (c-plane) and non polar (a-, m-plane) n-type 6H-SiC wafers. Ni/SiC ohmic contact was accomplished on the backside of the SiC wafers by thermal evaporation and annealed for 20minutes at $950^{\circ}C$ in mixture gas ($N_2$ 90% + $H_2$ balanced). The specific contact resistance was $3.6{\times}10^{-4}{\Omega}cm^2$ after annealing at $950^{\circ}C$. The XRD results of the alloyed contact layer show that formation of $NiSi_2$ layer might be responsible for the ohmic contact. The active rectifying electrode was formed by the same thermal evaporation of Ni thin film on topside of the SiC wafers and annealed for 5 minutes at $500^{\circ}C$ in mixture gas ($N_2$ 90% + $H_2$ balanced). The electrical properties of SBDs have been characterized by means of I-V and C-V curves. The forward voltage drop is about 0.95 V, 0.8 V and 0.8 V for c-, a- and m-plane SiC SBDs respectively. The ideality factor (${\eta}$) of all SBDs have been calculated from log(I)-V plot. The values of ideality factor were 1.46, 1.46 and 1.61 for c-, a- and m-plane SiC SBDs, respectively. The schottky barrier height (SBH) of all SBDs have been calculated from C-V curve. The values of SBH were 1.37 eV, 1.09 eV and 1.02 eV for c-, a- and m-plane SiC SBDs, respectively.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.346-349
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• 2011

In this paper, we design a perceptually invisible dot pattern layout and its recognition scheme, and we apply the recognition scheme into a smart self learning aid for interactive learning aid. To increase maximum information capacity and also increase robustness to the noises, we design a ECC (error correcting code) based dot pattern with directional vector indicator. To make a smart self-learning aid, we embed the micro dot pattern (20 information bit + 15 ECC bits + 9 layout information bit) using K ink (CMYK) and extract the dot pattern using IR (infrared) LED and IR filter based camera, which is embedded in the smart pen. The reason we use K ink is that K ink is a carbon based ink in nature, and carbon is easily recognized with IR even without light. After acquiring IR camera images for the dot patterns, we perform layout adjustment using the 9 layout information bit, and extract 20 information bits from 35 data bits which is composed of 20 information bits and 15 ECC bits. To embed and extract information bits, we use topology based dot pattern recognition scheme which is robust to geometric distortion which is very usual in camera based recognition scheme. Topology based pattern recognition traces next information bit symbols using topological distance measurement from the pivot information bit. We implemented and experimented with sample patterns, and it shows that we can achieve almost 99% recognition for our embedding patterns.

• International Journal of Computer Science & Network Security
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• v.22 no.9
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• pp.414-426
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• 2022

Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex - 5 and Xilinx Virtex - 7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2¹⁶³), GF(2²³³) and GF(2²⁸³). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex-5 and by 25.13% and 47.75% for Xilinx Virtex-7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex - 5 and Virtex - 7 over GF(2²³³) and GF(2²⁸³)are also very satisfactory.

• Journal of Chest Surgery
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• v.17 no.2
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• pp.184-188
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• 1984

As OHS is prevalent on whole world, LV-RA shunts once thought as quite rare congenital heart disease are reported frequently. Two cases of LV-RA shunts were operated at N.M.C. in 1983: One of them combined VSD, the other membranous ventricular septal aneurysm protruding into right atrial chamber. In case 1, which was diagnosed correctly, right atriotomy was enough to close the defect under ECC, but in case 2, which was misdiagnosed as ASD preoperatively, atriotomy was added to ventriculotomy. The LV-RA defects were closed by U-shaped direct suture with Teflon felt pledget. Postoperative course was uneventful in both of them.

• Honam Mathematical Journal
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• v.29 no.3
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• pp.415-425
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• 2007

The normal basis has the advantage that the result of squaring an element is simply the right cyclic shift of its coordinates in hardware implementation over finite fields. In particular, the optimal normal basis is the most efficient to hardware implementation over finite fields. In this paper, we propose an efficient parallel architecture which transforms the Gaussian normal basis multiplication in GF($2^m$) into the type-I optimal normal basis multiplication in GF($2^{mk}$), which is based on the palindromic representation of polynomials.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.928-931
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• 2003

This paper presents a digit-serial/parallel multiplier for finite fields GF(2m). The hardware requirements of the implemented multiplier are less than those of the existing multiplier of the same class, while processing time and area complexity. The implemented multiplier possesses the features of regularity and modularity. Thus, it is well suited to VLSI implementation. If the implemented digit-serial multiplier chooses the digit size D appropriately, it can meet the throughput requirement of a certain application with minimum hardware. The multipliers and squarers analyzed in this paper can be used efficiently for crypto processor in Elliptic Curve Cryptosystem.

• Journal of the Korea institute for structural maintenance and inspection
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• v.22 no.6
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• pp.16-23
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• 2018

In this study, Polydimethylsiloxane (PDMS) was applied to Strain Hardening Cement Composites (SHCC) for penetrating water repellency. The penetration depth of PDMS, strength of SHCC, and chloride ion penetration resistance of SHCC were investigated. As a result of measuring penetration depth of PDMS when applying different application method, it was confirmed that all methods satisfied the requirements of KS F 4930. Although the immersion method showed the largest penetration depth, the spray method was considered to be more appropriate considering the ease of field application. Compressive strength tests showed that the penetration depth of PDMS decreased as the compressive strength of SHCC increased. The compressive strength of M4-A and M4-B specimens with large PDMS penetration depths decreased by 9.6% and 8.0%, respectively, compared with those of M4 specimens produced without PDMS. Compressive strengths of the M1-A and M1-B specimens with small PDMS penetration depths were reduced by 4% and 2.2%, respectively, compared with the M1 specimen. As a result, it can be seen that the strength reduction rate of SHCC increases as the penetration depth of PDMS increases. The chlorine ion penetration tests showed that the chlorine ion penetration resistance increases with the penetration depth of PDMS.