• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.216-226
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• 2015

The neutral beam injection generate ultra-high temperature energy in the tokamak of nuclear fusion. The neutral beam injection make up arc power supply, filament power supply and acceleration & deceleration power supply. The arc power supply has characteristics of low voltage and high current. Arc power supply generate arc through constant output of voltage and current. So this paper proposed suitable buck converter for low voltage and high current. The proposed buck converter used parallel switch because it can be increased capacity and decrease conduction loss. When an arc generated, the neutral beam injection chamber occur high voltage. And it will break output capacitor of buck converter. Therefore the output capacitor was removed in the proposed converter. Thus the proposed converter should be designed for the characteristics of low voltage and high current. Also, the arc power supply should be guaranteed for system stability. The proposed parallel buck converter enables the system stability of the divided low output voltage and high current. The proposed converter with constant output be the most important design of the output inductor. In this paper, designed arc power supply verified operation of system and stability through simulation and prototype. After it is applied to the 288[kW] arc power supply for neutral beam injection.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.3
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• pp.91-98
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• 2003

The importance of improving the quality of electric power is being strongly raised, owing to an increasing use of sensitive and small-sized electronic devices and systems. The transient over-voltages on low-voltage power distribution systems are induced by direct or indirect lightning return strokes. These can cause damage and/or malfunction of the utility systems for home automation, office automation, factory automation, medical automation, etc. The behaviors of lightning overvoltages transferred through the transformer to the low-voltage distribution systems using a Marx generator were experimentally investigated. Furthermore, the coupling mechanisms of lightning overvoltages transferred to the low-voltage systems were clearly illustrated through a theoretical simulation using a Pspice program. The overvoltages in low-voltage ac power systems are rarely limited by the application of the surge arrester to the primary side of the distribution transformer. A superior surge protection scheme is to install surge protection devices at the service entrance switchboard and/or at the load devices in TN power systems.

• New & Renewable Energy
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• v.18 no.3
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• pp.32-42
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• 2022

Rapid spread of intermittent renewable energy has amplified the instability and uncertainty of power systems. The Korea Power Exchange (KPX) promoted efficient management by opening the power brokerage market in 2019. By combining small-scale intermittent renewable energy with a flexible facility through the power brokerage market, the KPX aims to develop a virtual power plant system that will allow the conversion of existing intermittent renewable energy into collective power plants. However, the participation rate of renewable power owners in the power brokerage market is relatively low because other markets such as the small solar power contract market or the Korea Electric Power Corporation power purchase agreement are more profitable. In this study, we used a choice experiment to determine the attributes affecting the participation rate in the power brokerage market for 113 renewable power owners and estimate the value of the power brokerage market. According to the estimation results, a low smart meter installation cost, low profit variations, long contract periods, and few clearances increased the probability of participation. Moreover, the average value of the power brokerage market was estimated to be 2.63 million KRW per power owner.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.131-135
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• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• Journal of Power Electronics
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• v.7 no.4
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• pp.328-335
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• 2007

A conventional Single-Stage Power-Factor-Correction (PFC) AC/DC converter has a link capacitor voltage problem under high line input and low load conditions. In this paper, this problem is analyzed by using the voltage conversion ratio of the DC/DC conversion cell. By applying this analysis, a new Single-Stage PFC AC/DC converter with a boost PFC cell integrated with a Voltage-Doubler Rectified Asymmetrical Half-Bridge (VDRAHB) is proposed. The proposed converter features good power factor correction, low current harmonic distortions, tight output regulations and low voltage of the link capacitor. An 85W prototype was implemented to show that it meets harmonic requirements and standards satisfactorily with near unity power factor and high efficiency over universal input.

• ETRI Journal
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• v.25 no.5
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• pp.321-327
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• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of International Academy of Physical Therapy Research
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• v.2 no.2
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• pp.318-323
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• 2011

The purpose of this study identify that spinal decompression therapy effect on and pain, length Of leg distance(LLD), and muscle power and flexibility in patient with low back pain. The participants is 20 female and male with low back pain, and participant assign to decompression therapy group and control group at random. The decompression therapy apply to 20 minute 3 time for a week during 4 weeks. The Measurement items is pain, LLD, and muscle power, flexibility. The comparison between the before and after was Wilcoxon's U test, and 2 group after spinal decompression therapy application compared Mann-Whithney U test. Spinal decompression therapy reduced statistically significance the pain, LLD, and increased statistically significance the muscle power and flexibility increased the muscle power(p<.05). This study showed that spinal decompression therapy does affect pain, LLD, and muscle power and flexibility in patient with low back pain.