• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1030-1033
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• 2002

This paper, a new simple controller operates in continuous conduction mode (CCM) for Boost power factor collection converter is introduced. The duty ratios are obtained by comparisons of a sensed signal from inductor current and a negative ramp carrier waveform in each switching period. By using the proposed controller, input voltage sensing, error amplifier in the current feedback loop, and analog multiplier／divider are not required, then, the control circuit implementation is very simple. To verify the proposed controller, the circuit simulation for Boost power factor correction converter was applied. For the results, the input current waveform was shaped to be closely sinusoidal, implying low THD.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1785-1792
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• 2000

In this paper multi-rate non-recursive architecture for CIC(Cascaded Integrator-Comb) decimation filters with an arbitrary factor is proposed. The CIC filters are widely used in high speed wireless communication systems since they have multiplier-less and multi-rate low-power structure. Even conventional non-recursive CIC structure is multi-rate this architecture can be structured only in case of M-th power-of-two decimation factor. This paper proposes that muli-rate non-recursive CIC architecture can be structured with an any decimation factor of product form. Power consumption of the proposed architecture is compared with that of the conventional non-recursion architecture.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.17-25
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• 2004

In this paper, we propose a new small swing domino logic for low-power consumption. To reduce the power consumption, both the precharge node and the output node swing the range from 0 to $V_{REF}$- $V_{THN}$, where $V_{REF}$=VDD-n $V_{THN}$ (n=1, 2, and 3). This can be done by adding the inverter structure on domino logic that allows a full swing or a small swing on its input terminal without leakage current. Compared to previous works, the proposed structure can save the power consumption of more than 30% for n=0, 1, 2, and 3 in the equation of $V_{REF}$=VDD-n $V_{THN}$. A multiplier applying the proposed domino logic has been designed and fabricated using a 0.35-${\mu}{\textrm}{m}$ n-well CMOS process under 3.3-V supply voltage. Compared with other previous works, it shows a 30% power reduction and a better feature in power-delay product.lay product.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.82-92
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• 2008

Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.

• Journal of IKEEE
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• v.19 no.3
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• pp.378-384
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• 2015

In conventional HEVC inverse core transform architectures, extra $n{\times}n$ inverse transform block is added to $2n{\times}2n$ inverse transform block, and it operates as one $2n{\times}2n$ inverse transform block or two $n{\times}n$ inverse transform blocks. Thus, same number of pixels are processed in the same time, but it suffers from increased hardware size due to extra $n{\times}n$ inverse transform block. To avoid this problem, a novel $8{\times}8$ HEVC inverse core transform architecture was proposed to eliminate extra $4{\times}4$ inverse transform block based on multiplier reuse. This paper extends this approach and proposes a novel HEVC $16{\times}16$ inverse core transform architecture. Its frame processing time is same in $4{\times}4$, $8{\times}8$, and $16{\times}16$ inverse core transforms, and reduces gate counts by 13%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.77-83
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• 2004

In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.