• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.45-52
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• 2008

We investigated the design of an RF-powered, wireless temperature sensor tag chip using $0.18-{\mu}m$ CMOS technology. The transponder generates its own power supply from small incident RF signal using Schottky diodes in voltage multiplier. Ambient temperature is measured using a new low-power temperature-to-voltage converter, and an 8-bit single-slope ADC converts the measured voltage to digital data. ASK demodulator and digital control are combined to identify unique transponder (ID) sent by base station for multi-transponder applications. The measurement of the temperature sensor tag chip showed a resolution of $0.64^{\circ}C/LSB$ in the range from $20^{\circ}C$ to $100^{\circ}C$, which is suitable for environmental temperature monitoring. The chip size is $1.1{\times}0.34mm^2$, and operates at clock frequency of 100 kHz while consuming $64{\mu}W$ power. The temperature sensor required a -11 dBm RF input power, supported a conversion rate of 12.5 k-samples/sec, and a maximum error of $0.5^{\circ}C$.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.1
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• pp.50-58
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• 2003

Among finite field arithmetic operations, the $AB^2$ operation is known as an efficient basic operation for public key cryptosystems over $GF(2^m)$,Division/Inversion is computed by performing the repetitive AB$^2$ multiplication. This paper presents two new $AB^2$algorithms and their systolic realizations in finite fields $GF(2^m)$.The proposed algorithms are based on the MSB-first scheme using standard basis representation and the proposed systolic architectures for $AB^2$ multiplication have a low hardware complexity and small latency compared to the conventional approaches. Additionally, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inversion architecture. Furthermore, these architectures will be utilized for the basic architecture of crypto-processor.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.101-108
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• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show $61.02\%$ cell area reduction comparison with those of the conventional multiplier butterfly structure. furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show $46.1\%$ cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.103-110
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• 2008

In this paper, an efficient butterfly structure for 8K/2K-Point Radix-4 FFT algorithm using CORDIC(coordinate rotation digital computer) is proposed. It is shown that CORDIC can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed CORDIC butterfly structure show 36.9% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 8K/2K-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 11.6% cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Journal of Sensor Science and Technology
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• v.15 no.4
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• pp.223-230
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• 2006

An FIR filter for digital voice signal processing has been designed and implemented using a microcontroller in implantable middle ear hearing devices (IMEHDs). The designed digital voice signal processing filter which has fast and accurate filtering operation and controllable filter characteristics has been implemented using a hardware multiplier and a direct memory access (DMA) in the low power microcontroller, MSP430F169. It has been confirmed that each of the implemented 6-orders Remez FIR filters with 1 channel and 2 channels can be applied to the voice signal processing module of IMEHDs based on the evaluation results of the filtering performance experiment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.17-24
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• 2008

This paper deals with a millimeter wave source which is utilizing sub-harmonic injection-synchronization technique. A 8.7GHz oscillator with MES-FET is fabricated, and is driven as a harmonic output oscillator at 17.4GHz by means of sub-harmonic injection-synchronization. The oscillator operates as a multiplier as well as oscillator in this system. Adopting this technique, we can obtain a high stable, high frequency millimeter wave source even though self-oscillating frequency of an oscillator is relatively low. In the experiments, the range of injection-synchronization is about 26MHz and is proportional to the input sub-harmonic power. From the spectrum analysis of the 2nd harmonic output. we blow that the phase noise of the harmonic oscillator is remarkably decreased.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.