• Title/Summary/Keyword: low-power dissipation

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2.5 GHZ SECOND-AND FOURTH-ORDER INDUCTORLESS RF BANDPASS FILTERS

  • Thanachayanont, Apinunt
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.86-89
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    • 2002
  • A new design approach for realising low-power low-voltage high-Q high-order RE bandpass filter is proposed. Based on the gyrator-C inductor topology, a 2$\^$nd/-order biquadratic bandpass filter can be realised by adding a series capacitor to the input port of the gyrator. High-Q 2$\^$nd/-order and 4$\^$th/-order fully differential RF bandpass filters operating in the 2.4-㎓ ISM (Industrial, scientific and medical) frequency band under a 2-V single power supply voltage with low power dissipation are reported.

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A kernel-based precomputation scheme for low-power design fo combinational circuits (저전력 논리 회로 설계를 위한 커널에 바탕을 둔 precomputation 알고리듬)

  • 최익성;류승현
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.11
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    • pp.12-19
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    • 1997
  • In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

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Seismic behavior of energy dissipation shear wall with CFST column elements

  • Su, Hao;Zhu Lihua;Wang, Yaohong;Feng, Lei;Gao, Zeyu;Guo, Yuchen;Meng, Longfei;Yuan, Hanquan
    • Steel and Composite Structures
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    • v.43 no.1
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    • pp.55-66
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    • 2022
  • To develop high-efficiency lateral force resistance components for high-rise buildings, a novel energy dissipation shear wall with concrete-filled steel tubular (CFST) column elements was proposed. An energy dissipation shear wall specimen with CFST column elements (GZSW) and an ordinary reinforced concrete shear wall (SW) were constructed, and experimented by low-cycle reversed loading. The mechanical characteristics of these two specimens, including the bearing capacity, ductility, energy dissipation, and stiffness degradation process, were analyzed. The finite-element model of the GZSW was established by ABAQUS. Based on this finite-element model, the effect of the placement of steel-plate energy dissipation connectors on the seismic performance of the shear wall was analyzed, and optimization was performed. The experiment results prove that, the GZSW exhibited a superior seismic performance in terms of bearing capacity, ductility, energy dissipation, and stiffness degradation, in comparison with the SW. The results calculated by the ABAQUS finite-elements model of GZSW corresponded well with the results of experiment, and it proved the rationality of the established finite-elements model. In addition, the optimal placement of the steel-plate energy dissipation connectors was obtained by ABAQUS.

Low-Power Cool Bypass Switch for Hot Spot Prevention in Photovoltaic Panels

  • Pennisi, Salvatore;Pulvirenti, Francesco;Scala, Amedeo La
    • ETRI Journal
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    • v.33 no.6
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    • pp.880-886
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    • 2011
  • With the introduction of high-current 8-inch solar cells, conventional Schottky bypass diodes, usually adopted in photovoltaic (PV) panels to prevent the hot spot phenomenon, are becoming ineffective as they cause relatively high voltage drops with associated undue power consumption. In this paper, we present the architecture of an active circuit that reduces the aforementioned power dissipation by profitably replacing the bypass diode through a power MOS switch with its embedded driving circuitry. Experimental prototypes were fabricated and tested, showing that the proposed solution allows a reduction of the power dissipation by more than 70% compared to conventional Schottky diodes. The whole circuit does not require a dedicated DC power and is fully compatible with standard CMOS technologies. This enables its integration, even directly on the panel, thereby opening new scenarios for next generation PV systems.

A New Scan Partition Scheme for Low-Power Embedded Systems

  • Kim, Hong-Sik;Kim, Cheong-Ghil;Kang, Sung-Ho
    • ETRI Journal
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    • v.30 no.3
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    • pp.412-420
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    • 2008
  • A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

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Code Visualization Approach for Low level Power Improvement via Identifying Performance Dissipation (성능 저하 식별을 통한 저전력 개선용 코드 가시화 방법)

  • An, Hyun Sik;Park, Bokyung;Kim, R.Young Chul;Kim, Ki Du
    • KIPS Transactions on Computer and Communication Systems
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    • v.9 no.10
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    • pp.213-220
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    • 2020
  • The power consumption and performance of hardware-based mobile and IoT embedded systems that require high specifications are one of the important issues of these systems. In particular, the problem of excessive power consumption is because it causes a problem of increasing heat generation and shortening the life of the device. In addition, in the same environment, software also needs to perform stable operation in limited power and memory, thereby increasing power consumption of the device. In order to solve these issues, we propose a Low level power improvement via identifying performance dissipation. The proposed method identifies complex modules (especially Cyclomatic complexity, Coupling & Cohesion) through code visualization, and helps to simplify low power code patterning and performance code. Therefore, through this method, it is possible to optimize the quality of the code by reducing power consumption and improving performance.

The A/D Converter for Low Power Multifunctional Sensor System (저전력 다기능 센서시스템 A/D Converter)

  • 박창규;김정규;이지원;김수성;최규훈
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1019-1022
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    • 2003
  • This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

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A 1.5V 2㎓ Low-Power Peak Detector (1.5V 2㎓ 저전력 피크 디텍터의 설계)

  • 박광민
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.149-152
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    • 2001
  • In this paper, a 1.5V 2㎓ low-power peak detector is presented. Analyzing the designed peak detector circuit which is composed with two NMOSs, two diodes, and two capacitors, the detection characteristic relationships are derived. The simulation results with SPICE for 2㎓ pulse signals and sinusoidal signals on the 1.5V supply voltages show the good detection characteristics for input signal levels of 50㎷~500㎷, and show very small power dissipation of 0.332㎽.

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Realization of 3.3V active low-pass filter using improved continuous-time current-mode CMOS integrator (개선된 연속시간 전류모드 CMOS 적분기를 이용한 3.3V 능동 저역필터 구현)

  • 방준호;조성익;이성룡;권오신;신홍규
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.4
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    • pp.52-62
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    • 1996
  • In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analog current-mode active filters was proposed. Compared to the current-mode integrator which was proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter was designed with the proposed current-mode integrator. The designed circuits were fabricated using the ORBIT's 1.2.mu.m double-poly double-metal CMOS n-well process. The experimental resutls of the active filter designed and fabricated for this research have shown that it has the performance of 44.5MHz cutoff frequency, 3.3mW power dissipation and the third-order active filter area was 0.12mm$^{2}$.

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A New State Assignment Technique for Testing and Low Power (테스팅 및 저진력을 고려한 상태할당 기술 개발)

  • Cho, Sang-Wook;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.10
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    • pp.9-16
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    • 2004
  • The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The algorithm minimizes the dependencies between groups of state variables are minimized and reduces switching activity by grouping the states depending on the state transition probability. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on the state variables. Experiment shows significant improvement in testabilities and Power dissipation for benchmark circuits.