• Transactions of the Korean Society of Mechanical Engineers
• /
• v.17 no.9
• /
• pp.2315-2328
• /
• 1993

The turbulence effect of particle deposition on a horizontal free-standing wafer in a vertical flow has been studied numerically by using the low-Reynolds-number k-.epsilon. turbulence model. For both the upper and lower surfaces of the wafer, predictions are made of the averaged particle deposition velocity and its radial distribution. Thus, it is now possible to obtain local information about the particle deposition on a free-standing wafer. The present result indicates that the particle deposition velocity on the lower surface of wafer is comparable to that on the upper one in the diffusion controlled deposition region in which the particle sizes are smaller than $0.1{\mu}m$. And it is found in this region that, compared to the laminar flow case, the averaged deposition velocity under the turbulent flow is about two times higher, and also that the local deposition velocity at the center of wafer is high equivalent to that the wafer edge.

• Proceedings of the KIEE Conference
• /
• 1992.07b
• /
• pp.850-853
• /
• 1992

A cryogenic electron cyclotron resonance plasma etching system has been built to study wafer-temperature in the silicon etching characteristics. The wafer temperature was controlled from -150 to +30 $^{\circ}C$ during etching using the liquid nitrogen cooled helium gas. Although silicon was etched isotropically in $SF_6$ plasma at room temperatures, we found that it is possible to suppress the etch undercut in Si by reducing a substrate temperature without side wall passivation. In addition, the selectivity of silicon to photoresist was improved considerably at a low wafer temperature. Etch rates, anisotropy and selectivity to photo resist are measured as a function of the wafer temperature in the region of -125 $\sim$ 25$^{\circ}C$ and rf bias power of 20W $\sim$ 80W.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.152-152
• /
• 2014

최근 반도체의 고집적화로 high dose implant 도입과 소자의 동작 특성 향상을 위한 low-k 물질 도입에 따라 다양한 주변 공정의 변화를 이끌고 있다. 이에 따라 반도체 제조의 핵심 공정 단계 중 하나인 ashing 단계에서 기존 성능 이상의 장비를 기대하고 있으며, 그것을 평가하기 위한 중요 요소로 uniformity와 fast stripping이 있다. 본 연구에서는 유체해석 시뮬레이션을 통해 450 mm ashing 챔버에서의 gas inlet baffle과 wafer stage 사이의 최적 거리를 예측했다. 우선적으로 시뮬레이션의 신뢰도를 높이기 위해 실험으로 측정한 300 mm ashing 결과와 유체해석 결과 molecular flux의 상관관계를 파악하여, 450 mm ashing 챔버의 최적 구조를 예측하였다. 선행 연구한 300 mm 시뮬레이션 결과를 바탕으로 이상적인 450 mm ashing 챔버를 설계하였다. 유체해석 결과는 동일한 형태의 수직형 구조 장비에서 baffle과 wafer stage 사이의 거리가 35 mm에서 60 mm일 때, 450 mm wafer surface 위에서 더욱 균일한 density 분포를 나타내었다. Reactant flux 분포는 거리가 60 mm에서 80 mm 사이일 경우 더 균일하게 나타났다. 그러므로, 450 mm 챔버에서 gas inlet baffle과 wafer stage 간격이 60 mm일 때 최적의 구조로 판단된다.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.10 no.1
• /
• pp.13-16
• /
• 2000

Progress in Si crystal and wafer technologies is discussed on single crystal growth, wafer fabrication, epitaxial growth, gettering, 300 mm and SOI. As for bulk crystal growth, the mechanism of grown-in defects (voids) formation, the succes of grown-in defect free crystal growth technology and nitrogen doped crystal are shown. New wafer fabrication technologies such as both-side mirror polishing and etchingless process have been developed. The epitaxial growth of SiGe/Si heterostructure for high speed bipolar device is treated. Gettering technology under low temperature process such as RTP is important, and also it is shown that IG effect for Ni could be predicted using computer simulation of precipitate density and size. The development of 300 mm wafer and SOI has made progress steadily.

• Journal of the Korean Ceramic Society
• /
• v.48 no.4
• /
• pp.312-315
• /
• 2011

The effect of slurry composition and wafer flatness on a material removal rate (MRR) and resulting surface roughness which are evaluation parameters to determine the CMP characteristics of the on-axis 6H-SiC substrate were systematically investigated. 2-inch SiC wafers were fabricated from the ingot grown by a conventional physical vapor transport (PVT) method were used for this study. The SiC substrate after the CMP process using slurry added oxidizers into slurry consisted of KOH-based colloidal silica and nano-size diamond particle exhibited the significant MRR value and a fine surface without any surface damages. SiC wafers with high bow value after the CMP process exhibited large variation in surface roughness value compared to wafer with low bow value. The CMPprocessed SiC wafer having a low bow value of 1im was observed to result in the Root-mean-square height (RMS) value of 2.747 A and the mean height (Ra) value of 2.147 A.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.839-844
• /
• 2003

This paper presents a method to segment wafer ID marks on poor quality images under uncontrolled lighting conditions of the semiconductor process. The active multiple templates matching method is suggested to search ID areas on wafers and segment them into meaningful regions and it would have been impossible to recognize characters using general OCR algorithms. This active template model is designed by applying a snake model that is used for active contour tracking. Active multiple template model searches character areas and segments them into single characters optimally, tracking each character that can vary in a flexible manner according to string configurations. Applying active multiple templates, the optimization of the snake energy is done using Greedy algorithm, to maximize its efficiency by automatically controlling each template gap. These vary according to the configuration of character string. Experimental results using wafer images from real FA environment are presented.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.19 no.5
• /
• pp.1319-1332
• /
• 1995

Numerical analysis was performed to characterize the particle deposition behavior on a horizontal free-standing wafer with thermophoretic effect under the turbulent flow field. A low Reynolds number k-.epsilon. turbulence model was used to analyze the turbulent flow field around the wafer, and the temperature field for the calculation of the thermophoretic effect was predicted from the energy equation introducing the eddy diffusivity concept. The deposition mechanisms considered were convection, diffusion, sedimentation, turbulence and thermophoresis. For both the upper and lower surfaces of the wafer, the averaged particle deposition velocities and their radial distributions were calculated and compared with the laminar flow results and available experimental data. It was shown by the calculated averaged particle deposition velocities on the upper surface of the wafer that the deposition-free zone, where the deposition velocite is lower than 10$^{-5}$ cm/s, exists between 0.096 .mu.m and 1.6 .mu.m through the influence of thermophoresis with positive temperature difference of 10 K between the wafer and the ambient air. As for the calsulated local deposition velocities, for small particle sizes d$_{p}$<0.05 .mu.m, the deposition velocity is higher at the center of the wafer than at the wafer edge, whereas for particle size of d$_{p}$ = 2.0 .mu.m the deposition takes place mainly on the inside area of the wafer. Finally, an approximate model for calculating the deposition velocities was recommended and the calculated deposition velocity results were compared with the present numerical solutions, those of Schmidt et al.'s model and the experimental data of Opiolka et al.. It is shown by the comparison that the results of the recommended model agree better with the numerical solutions and Opiolka et al.'s data than those of Schmidt's simple model.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.3
• /
• pp.37-41
• /
• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Current Photovoltaic Research
• /
• v.5 no.2
• /
• pp.59-62
• /
• 2017

Surface texturing is affected the uniformity and size of pyramid with saw mark defect density. To analysis the influence of the saw mark defect density, we textured various si wafer. When the texturing process proceeds without the saw mark removal, silicon wafer of low-saw mark defect density showed small pyramid size of $3.5{\mu}m$ with the lowest average value of the reflectance of 10.6%. When texturing carried out after removal of the saw mark using the TMAH solution, we obtained a reflectance of about 11% and the large pyramid size of $5{\mu}m$. As a result, saw mark wafers showed a better pyramid structure than saw mark-free wafer. This result showed that saw mark can take place more smooth etching by the KOH solution and saw mark-free wafer is determined to be a factor that have a higher reflectance and a large pyramid.

• Proceedings of the KSME Conference
• /
• 2007.05b
• /
• pp.2032-2037
• /
• 2007

Numerical analysis was conducted to investigate the atomic layer deposition(ALD) of silicon nitride using silane and ammonia as precursors. The present study simulated the surface reactions for as-deposited $Si_3N_4$ as well as the kinetics for the reactions of $SiH_4$ and $NH_3$on the semiconductor wafer. The present numerical results showed that the ALD process is dependent on the activation constant. It was also shown that the low activation constant leads to the self-limiting reaction required for the ALD process. The inlet and wafer temperatures were 473 K and 823 K, respectively. The system pressure is 2 Torr.