• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.34.2-34.2
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• 2011

The demand for Ru has been increasing in the electronic, chemical and semiconductor industry. Chemical mechanical planarization (CMP) is one of the fabrication processes for electrode formation and barrier layer removal. The abrasive particles can be easily contaminated on the top surface during the CMP process. This can induce adverse effects on subsequent patterning and film deposition processes. In this study, a post Ru CMP cleaning solution was formulated by using sodium periodate as an etchant and citric acid to modify the zeta potential of alumina particles and Ru surfaces. Ru film (150 nm thickness) was deposited on tetraethylorthosilicate (TEOS) films by the atomic layer deposition method. Ru wafers were cut into $2.0{\times}2.0$ cm pieces for the surface analysis and used for estimating PRE. A laser zeta potential analyzer (LEZA-600, Otsuka Electronics Co., Japan) was used to obtain the zeta potentials of alumina particles and the Ru surface. A contact angle analyzer (Phoenix 300, SEO, Korea) was used to measure the contact angle of the Ru surface. The adhesion force between an alumina particle and Ru wafer surface was measured by an atomic force microscope (AFM, XE-100, Park Systems, Korea). In a solution with citric acid, the zeta potential of the alumina surface was changed to a negative value due to the adsorption of negative citrate ions. However, the hydrous Ru oxide, which has positive surface charge, could be formed on Ru surface in citric acid solution at pH 6 and 8. At pH 6 and 8, relatively low particle removal efficiency was observed in citric acid solution due to the attractive force between the Ru surface and particles. At pH 10, the lowest adhesion force and highest cleaning efficiency were measured due to the repulsive force between the contaminated alumina particle and the Ru surface. The highest PRE was achieved in citric acid solution with NaIO4 below 0.01 M at pH 10.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.254-254
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• 2011

The memories with nano-particles are very attractive because they are promising candidates for low operating voltage, long retention time and fast program/erase speed. In recent, various nano-floating gate memories with metal-oxide nanocrystals embedded in organic and inorganic layers have been reported. Because of the carrier generation in semiconductor, induced photon pulse enhanced the program/erase speed of memory device. We studied photo-induced electrical properties of these metal-oxide nanocrystal memory devices. At first, 2~10-nm-thick Sn and In metals were deposited by using thermal evaporation onto Si wafer including a channel with $n^+$ poly-Si source/drain in which the length and width are 10 ${\mu}m$ each. Then, a poly-amic-acid (PAA) was spin coated on the deposited Sn film. The PAA precursor used in this study was prepared by dissolving biphenyl-tetracarboxylic dianhydride-phenylene diamine (BPDA-PDA) commercial polyamic acid in N-methyl-2-pyrrolidon (NMP). Then the samples were cured at 400$^{\circ}C$ for 1 hour in N atmosphere after drying at 135$^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was followed by using a thermal evaporator, and then the gate electrode was defined by photolithography and etching. The electrical properties were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. Also, the optical pulse for the study on photo-induced electrical properties was applied by Xeon lamp light source and a monochromator system.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.7
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• pp.571-574
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• 2010

Surface recombination loss should be reduced for high efficiency of solar cells. To reduce this loss, the BSF (back surface field) is used. The BSF on the back of the p-type wafer forms a p+layer, which prevents the activity of electrons of the p-area for the rear recombination. As a result, the leakage current is reduced and the rear-contact has a good Ohmic contact. Therefore, the open-circuit-voltage (Voc) and fill factor (FF) of solar cells are increased. This paper investigates the formation of the rear contact process by comparing aluminum-paste (Al-paste) with pure aluminum-metal(99.9%). Under the vacuum evaporation process, pure aluminum-metal(99.9%) provides high conductivity and low contact resistance of $4.2\;m{\Omega}cm$, but It is difficult to apply the standard industrial process to it because high vacuum is needed, and it's more expensive than the commercial equipment. On the other hand, using the Al-paste process by screen printing is simple for the formation of metal contact, and it is possible to produce the standard industrial process. However, Al-paste used in screen printing is lower than the conductivity of pure aluminum-metal(99.9) because of its mass glass frit. In this study, contact resistances were measured by a 4-point probe. The contact resistance of pure aluminum-metal was $4.2\;m{\Omega}cm$ and that of Al-paste was $35.69\;m{\Omega}cm$. Then the rear contact was analyzed by scanning electron microscope (SEM).

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.123-123
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• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.25-29
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• 2015

Demand for a low-cost, high-throughput, and high-resolution patterning method for fabricating devices continues to increase. The roll-to-roll (R2R) imprint lithography technique has received a great deal of attention as a means of fabricating next-generation devices. In this paper, we propose a fabrication method for polymeric planar lightwave circuit (PLC) devices that uses R2R imprint lithography. The proposed technique uses an elastomeric polydimethylsiloxane (PDMS) mold. A Si wafer with micro patterns is used as the Si master. The PDMS mold is then replicated from the Si master. By applying a precise web tension and at a given web speed, we fabricated a micro-patterned PLC device. The insertion losses were 4.0 dB for a $1{\times}2$ optical splitter. As such, the proposed method of fabricating a PLC device by the R2R process was shown to be an effective solution.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.34 no.1
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• pp.73-76
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• 2010

The issue of inspection and characterization of microstructures has emerged as a major consideration in design, fabrication, and detection of MEMS devices. However, the conventional measurement techniques, including scanning electron microscopy (SEM) imaging, atomic force microscopy (AFM) scanning, and mechanical surface profiler, require often destructive process or may be difficult to measure with a wafer scale. In this paper, we characterize the surface profiles of microstructures using an optical scanner based on a DVD pick-up module. Scanning images of the microstructures are successfully generated using the intensity of reflected light from different depths of the surface profiles, based on the focus error signal (FES) from photodiodes. It is shown that the proposed optical scanner can be used as an alternative measurement system with high performance and low cost, compared to conventional measurement techniques.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.10
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• pp.113-123
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• 1990

Tungsten film was deposited on the single crystal silicon wafer in a low pressure chemical vapor deposition reactor from silane and tungsten hexafluoride in the temperature range of $250-400^{\circ}C$ Deposition rate was found to be determined by the mass transfer rate of reactants from the gas phase to the safter surface. It was found out that tungsten films deposited contained about 3 atomic $\%$ of silicon and that the crystallinity and the grain size increased as the deposition temperature was increased. The resistivity of the film was measured to be in the range of $7~25{\mu}{\Omega}-cm$ and decreased with increasing deposition temperature. The adhesion of the tungsten film on a silicon surface was measured by the tape peel off test and it was improved with increasing deposition temperature. From the analysis of the gas composition, the reaction pathway to form $SiF_{4}$ and $H_{2}$ was found to be more favorable than HF formation.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.51-57
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• 1999

In this paper, an adaptive thresholding of the nonuniformly contrasted images is proposed through using the contrast pre-enhancement of the local regions and the bilinear interpolation between the local threshold values. The nonuniformly contrasted image is decomposed into 9${\times}$9 sized local regions, and the contrast is enhanced by intensifying the gray level difference of each low contrasted or blurred region. Optimal threshold values are obtained by iterative method from the gray level distribution of each contrast-enhanced local region. Discontinuities are reduced at the region of interest or at the characters by using bilinear interpolation between the neighboring threshold surfaces. Character recognition experiments are conducted using backpropagation neural network on the characters extracted from the nonuniformly contrasted document, PCB, and wafer images binarized through using the proposed thresholding and the conventional thresholding methods, and the results prove the relative effectiveness of the proposed scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.112-117
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• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

• Journal of the Korean Ceramic Society
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• v.39 no.4
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• pp.377-385
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• 2002

The possibility of $ZrO_2$ thin film as insulator for Metal-Ferroelectric-Insulator-Semiconductor(MFIS) structure was investgated. $SrBi_2Ta_2O_9$ and $SrBi_2Ta_2O_9$(SBT) thin films were deposited on P-type Si(111) wafer by R. F. magnetron sputtering method. The electrical properties of MFIS gate were relatively improved by inserting the $ZrO_2$ buffer layer. The window memory increased from 0.5 to 2.2V in the applied gate voltage range of 3-9V when the thickness of SBT film increased from 160 to 220nm with 20nm thick $ZrO_2$. The maximum value of window memory is 2.2V in Pt/SBT(160nm)/$ZrO_2$(20nm)/Si structure with the optimum thickness of $ZrO_2$. These memory windows are sufficient for practical application of NDRO-FRAM operating at low voltage.