• Journal of Sensor Science and Technology
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• v.11 no.1
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• pp.54-59
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• 2002

This paper describes a new process technique for batch process of SOI(Si-on-Insulator) structures with buried cavities for MEMS(Micro Electro Mechanical System) applications by SDB(Si-wafer Direct Bonding) technology and electrochemical etch-stop. A low-cost electrochemical etch-stop method is used to control accurately the thickness of SOI. The cavities were made on the upper handling wafer by Si anisotropic etching. Two wafers are bonded with an intermediate insulating oxide layer. After high-temperature annealing($1000^{\circ}C$, 60 min), the SDB SOI structure with buried cavities was thinned by electrochemical etch-stop. The surface of the fabricated SDB SOI structure have more roughness that of lapping and polishing by mechanical method. This SDB SOI structure with buried cavities will provide a powerful and versatile substrate for novel microsensors arid microactuators.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.6-11
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• 2011

We have developed dissolved ozone decompose system in the used ozonated water for the semiconductor and LCD fabrication processes, which will be base of obtaining core process technology in the high performance, low price semiconductor and LCD fabrications. Using this technology, it is possible for the semiconductor wafer and LCD planer to process more rapid and chip, and productivity will be improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.537-537
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• 2008

Copper (Cu) has been widely used for interconnection structure in intergrated circuits because of its properties such as a low resistance and high resistance to electromigration compared with aluminuim. Damascene processing for the interconnection structure utilizes 2-steps chemical mechanical polishing(CMP). After polishing, the removal of abrasive particles on the surfaces becomes as important as the polishing process. In the paper, buffing process for the removal of colloidal silica from polished Cu wafer was proposed and demonstrated.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.330-333
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• 2005

The fabrication of mold fur nano imprint lithography (NIL) is experimentally reported using the scanning probe lithography (SPL) technique, instead of the conventional I-beam lithography technique. The nanometer scale patterning structure is fabricated by the localized generation of oxide patterning on the silicon (100) wafer surface with a thin oxide layer, The fabrication method is based on the contact mode of scanning probe microscope (SPM) in air, The precision cleaning process is also performed to reach the low roughness value of $R_{rms}=0.084 nm$, which is important to increase the reproducibility of patterning. The height and width of the oxide dot are generated to be 15.667 nm and 209.5 nm, respectively, by applying 17 V during 350 ms.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.371.2-371.2
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• 2016

Graphene electronics is one of the promising technologies for the next generation electronic devices due to the outstanding properties such as conductivity, high carrier mobility, mechanical, and optical properties along with extended applications using 2 dimensional heterostructures. However, large contact resistance between metal and graphene is one of the major obstacles for commercial application of graphene electronics. In order to achieve low contact resistance, numerous researches have been conducted such as gentle plasma treatment, ultraviolet ozone (UVO) treatment, annealing treatment, and one-dimensional graphene edge contact. In this report, we suggest a fabrication method of one-dimensional graphene metal edge contact without using graphene exfoliation. Graphene is grown on Cu foil by low pressure chemical vapor deposition. Then, the graphene is transferred on $SiO_2/Si$ wafer. The patterning of graphene channel and metal electrode is done by photolithography. $O_2$ plasma is applied to etch out the exposed graphene and then Ti/Au is deposited. As a result, the one-dimensional edge contact geometry is built between metal and graphene. The contact resistance of the fabricated one-dimensional metal-graphene edge contact is compared with the contact resistance of vertically stacked conventional metal-graphene contact.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.444-445
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• 2009

The metallic contact system of silicon solar cell must have several properties, such as low contact resistance, easy application and good adhesion. Ni is shown to be a suitable barrier to Cu diffusion as well as desirable contact metal to silicon. Nickel monosilicide(NiSi) has been suggested as a suitable silicide due to its lower resistivity, lower sintering temperature and lower layer stress than $TiSi_2$. Copper and Silver can be plated by electro & light-induced plating method. Light-induced plating makes use the photovoltaic effect of solar cell to deposit the metal on the front contact. The cell is immersed into the electrolytic plating bath and irradiated at the front side by light source, which leads to a current density in the front side grid. Electroless plated Ni/ Electro&light-induced plated Cu/ Light-induced plated Ag contact solar cells result in an energy conversion efficiency of 16.446 % on $0.2\sim0.6\;{\Omega}{\cdot}cm$, $20\;\times\;20\;mm^2$, CZ(Czochralski) wafer.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1384-1385
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• 2006

Platinum is a candidate of top and bottom electrode in ferroelectric random access memory and dynamic random access memory. High dielectric materials and ferroelectric materials were generally patterned by plasma etching, however, the low etch rate and low etching profile were repoted. We proposed the damascene process of high dielectric materials and ferroelectric materials for patterning process through the chemical mechanical polishing process. At this time, platinum as a top electrode was used for the stopper for the end-point detection as Igarashi model. Therefore, the control of removal rate in platinum chemical mechanical polishing process was required. In this study, an addition of $H_{2}O_{2}$ oxidizer to alumina slurry could control the removal rate of platinum. The removal rate of platinum rapidly increased with an addition of 10wt% $H_{2}O_{2}$ oxidizer from 24.81nm/min to 113.59nm/min. Within-wafer non-uniformity of platinum after chemical mechanical polishing process was 9.93% with an addition of 5wt% $H_{2}O_{2}$ oxidizer.

• Korean Journal of Materials Research
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• v.16 no.2
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• pp.99-105
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• 2006

This paper reports an improved bonding method using the IPA (isopropyl alcohol) assisted low-temperature bonding process for the PMMA (polymethylmethacrylate) micro CE (capillary electrophoresis) chip. There is a problem about channel deformations during the conventional processes such as thermal bonding and solvent bonding methods. The bonding test using an IPA showed good results without channel deformations over 4 inch PMMA wafer at $60^{\circ}C$ and 1.3 bar for 10 minutes. The mechanism of IPA bonding was attributed to the formation of a small amount of vaporized acetone made from the oxidized IPA which allows to solvent bonding. To verify the usefulness of the IPA assisted low-temperature bonding process, the PMMA micro CE chip which had a $45{\mu}m$ channel height was fabricated by hot embossing process. A functional test of the fabricated CE chip was demonstrated by the separation of fluorescein and dichlorofluorescein. Any leakage of liquids was not observed during the test and the electropherogram result was successfully achieved. An IPA assisted low-temperature bonding process could be an easy and effective way to fabricate the PMMA micro CE chip and would help to increase the yield.

• Applied Science and Convergence Technology
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• v.26 no.4
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• pp.79-85
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• 2017

The crack-free AlGaN template has been successfully grown by using selective area growth with triangular GaN facet. The triangular GaN stripe structure was obtained by vertical growth rate enhanced mode with low growth temperature of $950^{\circ}C$ and high growth pressure of 500 torr. The lateral growth rate enhanced mode of AlGaN for crack-free and flat surface was also investigated. Low pressure of 30 torr and high V/III ratio of 4400 were favorable for lateral growth of AlGaN. It was confirmed that the $4{\mu}m$ -thick $Al_{0.2}Ga_{0.8}N$ was crack-free over entire 2-inch wafer. The dislocation density of $Al_{0.2}Ga_{0.8}N$ was as low as ${\sim}7.6{\times}10^8/cm^2$ measured by cathodoluminescence. Based on the high quality AlGaN with low dislocation density, the ultraviolet laser diode epitaxy with cladding, waveguide and GaN/AlGaN multiple quantum well (MQW) was grown by metalorganic chemical vapor deposition. The stimulated emission at 349 nm with full width at half maximum of 1.8 nm from the MQW was observed through optical pumping experiment with 193 nm KrF laser. We also have fabricated the deep ridge type ultraviolet laser diode (UV-LD) with $5{\mu}m-wide$ and $700{\mu}m-long$ cavity for electrical properties. The turn on voltage was below 5 V and the resistance was ${\sim}55{\Omega}$ at applied voltage of 10 V. The amplified spontaneous emission spectrum of UV-LD was also observed from pulsed current injection.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.332-333
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• 2008

DC magnetron sputtering was used to deposit p-type polycrystalline silicon on n-type Si(100) wafer. The influence of film microstructure properties on deposition parameters (DC power, substrate temperature, pressure) was investigated. The substrate temperature and pressure have the important influence on depositing the poly-Si thin films. Smooth ploy-Si films were obtained in (331) orientation and the average grain sizes are ranged in 25-30nm. The grain sizes of films deposited at low pressure of 10mTorr are a little larger than those deposited at high pressure of 15mTorr.