• 한국정밀공학회지
• /
• 제26권12호
• /
• pp.9-17
• /
• 2009

• 반도체디스플레이기술학회지
• /
• 제13권4호
• /
• pp.83-90
• /
• 2014

This paper is about the yield rate of lower temperature furnace for wafer heat-treatment. The flat-zone that the temperature in furnace has uniform distribution specific area is the significant variable to the yield rate. In this study, we researched about the ways how to widen the flat zone in the furnace using CFD. As a result, we confirmed that the characteristic of the flat-zone was changed when SCU(Super Cooling Unit) was used. We considered temperature control with above.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2005년도 추계학술대회 논문집
• /
• pp.882-884
• /
• 2005

A new rectangular shape microlens array having high sag for solid-state lighting is presented. Proposed microlens, which has high sag, over $375{\mu}m$ and large diameter, over 3 mm can enormously enhance output optical extraction efficiency. Rectangular shape of microlens can maximize the fill factor of light-emitting-diode (LED) package and minimize the optical loss at the same time. This wafer level microlens array is fabricated on LED package. It has many advantages in optical properties, low cost, high aligning accuracy, and mass production.

• 대한산업공학회지
• /
• 제38권1호
• /
• pp.46-56
• /
• 2012

The purpose of virtual metrology (VM) in semiconductor manufacturing is to predict every wafer's metrological values based on its process equipment data without an actual metrology. In this paper, we propose novelty detection-based reliability estimation models for VM in order to support flexible utilization of VM results. Because the proposed model can not only estimate the reliability of VM, but also identify suspicious process variables lowering the reliability, quality control actions can be taken selectively based on the reliance level and its causes. Based on the preliminary experimental results with actual semiconductor manufacturing process data, our models can successfully give a high reliance level to the wafers with small prediction errors and a low reliance level to the wafers with large prediction errors. In addition, our proposed model can give more detailed information by identifying the critical process variables and their relative impacts on the low reliability.

• 폴리머
• /
• 제31권5호
• /
• pp.447-453
• /
• 2007

본 연구에서는 재결정 PLGA 분말을 진공 건조 방법을 사용하여 제조하였다. 5-FU가 함유된 PLGA 웨이퍼를 이용한 조절된 방출을 위하여 재결정 PLGA 분말의 응용성을 연구하기 위하여 세 종류의 웨이퍼를 제조하였다; 1) 순수한 PLGA, 2) 재결정 PLGA, 및 3) 순수한PLGA와 재결정 PLGA의 혼합(4 : 1, 1 : 1 및 1 : 4). 순수한 PLGA와 재결정 PLGA 분말은 NMR, IR과 GPC를 이용하여 비교 분석하였다. 주사전자현미경을 이용하여 제조한 웨이퍼 의 표면과 단면의 형태학적 차이를 관찰하였다. 웨이퍼로부터 방출된 5-FU의 방출거동은 HPLC를 이용하여 측정하였다. 5-FU/재결정 PLGA 웨이퍼는 5-FU/순수한 PLGA 웨이퍼에 비교하여 낮은 초기 방출과 지속적 방출거동을 갖는 것을 확인하였다. 순수한 PLGA/재결정 PLGA의 비율은 조절된 방출거동을 갖게 할 수 있음을 볼 수 있었다.

• 한국전기전자재료학회논문지
• /
• 제26권12호
• /
• pp.858-862
• /
• 2013

The front electrode should be used to make solar cell panel so as to collect electron. The front electrode is used by paste type, printed on the Si-solar cell wafer and sintered at about $800^{\circ}C$. The paste is composed Ag powder and glass frit which make the ohmic contact between Ag electrode and n-type semiconductor layer. From the previous study, the Ag electrodes which used two commercial glass frit of Bi-system were so different on the interface resistance. The main composition of them was Bi-Zn-B-Si-O and few additives added in one of them. In this study, glass frit was made with the ratio of $Bi_2O_3$ and ZnO on the main composition, and then paste using glass frit was prepared respectively. And, also, the paste using the glass frit added oxide additives were prepared. The change of interface resistance was not large with the ratio of $Bi_2O_3$ and ZnO. In the case of G6 glass frit, 78 wt% $Bi_2O_3$ addition, the interface resistance was $190{\Omega}$ and most low. In the glass frit added oxide, the case of Ca increased over 10 times than it of G6 glass frit on the interface resistance. It was thaught that after sintering, Ca added glass frit was not flowed to the interface between Ag electrode and wafer but was in the Ag electrode.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
• /
• pp.393-393
• /
• 2012

Optically active nanostructures such as subwavelength moth-eye antireflective structures or surface enhanced Raman spectroscopy (SERS) active structures have been demonstrated to provide the effective suppression of unwanted reflections as in subwavelength structure (SWS) or effective enhancement of selective signals as in SERS. While various nanopatterning techniques such as photolithography, electron-beam lithography, wafer level nanoimprinting lithography, and interference lithography can be employed to fabricate these nanostructures, roll-to-roll (R2R) nanoimprinting is gaining interests due to its low cost, continuous, and scalable process. R2R nanoimprinting requires a master to produce a stamp that can be wrapped around a quartz roller for repeated nanoimprinting process. Among many possibilities, two different types of mask can be employed to fabricate optically active nanostructures. One is self-assembled Au nanoparticles on Si substrate by depositing Au film with sputtering followed by annealing process. The other is monolayer silica particles dissolved in ethanol spread on the wafer by spin-coating method. The process is optimized by considering the density of Au and silica nano particles, depth and shape of the patterns. The depth of the pattern can be controlled with dry etch process using reactive ion etching (RIE) with the mixture of SF6 and CHF3. The resultant nanostructures are characterized for their reflectance using UV-Vis-NIR spectrophotometer (Agilent technology, Cary 5000) and for surface morphology using scanning electron microscope (SEM, JEOL JSM-7100F). Once optimized, these optically active nanostructures can be used to replicate with roll-to-roll process or soft lithography for various applications including displays, solar cells, and biosensors.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
• /
• pp.226-226
• /
• 2013

Si is a dominant solar material, which is the second most abundant element in the earth giving a benefit in the aspect in cost with low toxicity. However, the inherent limit of Si has an indirect band gap of 1.1 eV resulting in the limited optical absorption. Therefore, a critical issue has been raised to increase the utilization of the incident light into the Si absorber. The enhancement of light absorption is a crucial to improve the performances and thus relieves the cost burden of Si photovoltaics. For the optical aspect, an efficient design of a front surface, where the incident light comes in, has been intensively investigated to improve the performance of photon absorption. Lambertian light trapping can be attained when the light active surface is ideally rough to increase the optical length by about 50 compared to a planar substrate. This suggests that an efficient design may reduce thickness of the Si absorber from the conventional 100~300 ${\mu}m$ to less than 3 ${\mu}m$. Theoretically, a hole-array structure satisfies an equivalent efficiency of c-Si with only one-twelfth mass and one-sixth thickness. Various approaches have been applied to improve the incident light utilization in a Si absorber using textured structures, periodic gratings, photonic crystals, and nanorod arrays. We have designed hole and pillar structured Si absorbers. Four-different Si absorbers have been simultaneously fabricated on an identical Si wafer with hole arrays or pillar arrays at a fixed depth of 2 ${\mu}m$. We have found that the significant enhanced solar cell performances both for the hole arrayed and pillar arrayed Si absorbers compared to that of a planar Si wafer resulting from the effective improvement in the quantum efficiencies.

• 전자공학회논문지
• /
• 제50권9호
• /
• pp.60-67
• /
• 2013

다양한 Intellectual Property(IP)로 이루어진 복잡한 SoC 테스트에 있어 테스트 비용 절감은 필수적이다. 본 논문에서는 IEEE Std. 1500과 IEEE Std. 1149.7 인터페이스를 사용하여 적은 수의 핀 수로 IP 기반의 System-on-a-Chip(SoC) 테스트를 가능케 하는 테스트 구조를 제안한다. IEEE Std. 1500은 IP 기반의 SoC 테스트에 있어 각 IP를 테스트할 수 있는 독립된 접근 경로를 제공한다. 본 논문에서는 이러한 독립된 테스트 경로를 IEEE Std. 1149.7로 제어 가능하도록 구성함으로서 SoC의 테스트 핀 수를 2 핀으로 줄일 수 있게 한다. 본 기술은 Wafer 및 Package 수준 테스트에 요구되는 테스트 핀 수를 줄임으로서 동시에 테스트 가능한 대상회로의 수를 늘릴 수 있고, 결과적으로 전체적인 양산 테스트 비용을 크게 절감할 수 있게 한다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2009년도 제38회 동계학술대회 초록집
• /
• pp.322-322
• /
• 2010

For boron doping on n-type silicon wafer, around $1,000^{\circ}C$ doping temperature is required, because of the relatively low solubility of boron in a crystalline silicon comparing to the phosphorus case. Boron doping by fiber laser annealing and lamp furnace heat treatment were carried out for the uniformly deposited p-a-Si:H layer. Since the uniformly deposited p-a-Si:H layer by cluster is highly needed to be doped with high temperature heat treatment. Amorphous silicon layer absorption range for fiber laser did not match well to be directly annealed. To improve the annealing effect, we introduce additional lamp furnace heat treatment. For p-a-Si:H layer with the ratio of $SiH_4:B_2H_6:H_2$=30:30:120, at $200^{\circ}C$, 50 W power, 0.2 Torr for 30 min. $20\;mm\;{\times}\;20\;mm$ size fiber laser cut wafers were activated by Q-switched fiber laser (1,064 nm) with different sets of power levels and periods, and for the lamp furnace annealing, $980^{\circ}C$ for 30 min heat treatment were implemented. To make the sheet resistance expectable and uniform as important processes for the $p^+$ layer on a polished n-type silicon wafer of (100) plane, the Q-switched fiber laser used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the fiber laser treatment showed the trade-offs between the lifetime and the sheet resistance as $100\;{\omega}/sq.$ and $11.8\;{\mu}s$ vs. $17\;{\omega}/sq.$ and $8.2\;{\mu}s$. Diode level device was made to confirm the electrical properties of these experimental results by measuring C-V(-F), I-V(-T) characteristics. Uniform and expectable boron heavy doped layers by fiber laser and lamp furnace are not only basic and essential conditions for the n-type crystalline silicon solar cell fabrication processes, but also the controllable doping concentration and depth can be established according to the deposition conditions of layers.