• ETRI Journal
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• v.35 no.2
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• pp.336-339
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• 2013

To enhance the symbol error rate (SER) performance of the two-way relay channels with physical layer network coding, this letter proposes a relay selection scheme, in which the relay with the maximal minimum distance between different points in its constellation among all relays is selected to assist two-way transmissions. We give the closed-form expression of minimum distance for binary phase-shift keying and quadrature phase-shift keying. Additionally, we design a low-complexity method for higher-order modulations based on look-up tables. Simulation results show that the proposed scheme improves the SER performance for two-way relay networks.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.438-451
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• 1994

A low complexity, fault detecting computer architecture for utilisation in programmable logic controllers is designed. The cyclic operating mode of PLCs and a specification level, graphical programming paradigm based on the interconnection of application oriented standard software function modules are architecturally supported. Thus, by design, there is no semantic gap between the programming and machine execution levels enabling the safety licensing of application software by an extremely simple, but rigorous method, viz, diverse back translation.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.21 no.45
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• pp.319-328
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• 1998

In this paper, the design of ALT(Accelerated Life Test) requires a sampling plan based on failure-censored(Type II censored) ALT with lognormal life distribution. Specially the environmental effect of products has been emphasized, so we considered the upper life limit as well as lower life limit in the ALT sampling plan. The optimal plan with a high stress and a low stress is used as test plan, and the total sample size for test and lot acceptability constant which minimize an asymptotic variance of maximum likelihood estimator of assumed model parameters and satisfy the given producer's risk and customer's risk are drawn out. These values can be acquired by means of the computer program that we coded for resolving the difficulty and complexity of calculation.

• Proceedings of the KIEE Conference
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• 2000.11b
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• pp.348-351
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• 2000

There have been significant advances in thyratron performance in recent years. these advanced waveforms have increased the complexity and cost of drive circuits. Thyratrons can reliably switch anode voltages up to 40kV and conduct peak currents up to 10kA or more. So stable thyratron drivers are essential for reliable high voltage pulse modulators. In order to operate thyratron well, thyratron driver need high repetition rate, fast rising time and low jitter. In this paper, used power MOSFET/transformer combinations. Designed thyratron driver is satisfied requirements and experimental results are presented to confirm.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.107-112
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.

• Journal of Power Electronics
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• v.10 no.4
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• pp.365-373
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• 2010

This paper proposes a hybrid single carrier sinusoidal modulation suitable for multiphase multilevel inverters. Multiphase multilevel inverters are controlled by hybrid modulation to provide multiphase variable voltage and a variable frequency supply. The proposed modulation combines the benefits of fundamental frequency modulation and single carrier sinusoidal modulation (SC-SPWM) strategies. The main characteristics of hybrid modulation are a reduction in switching losses and improved harmonic performance. The proposed algorithm can be applied to cascaded multilevel inverter topologies. It has low computational complexity and it is suitable for hardware implementations. SC-SPWM and its base modulation design are implemented on a TMS320F2407 digital signal processor (DSP). A Complex Programmable Logic Device realizes the hybrid PWM algorithm and it is integrated with a DSP processor for hybrid SC-SPWM generation. The feasibility of this hybrid modulation is verified by spectral analysis, power loss analysis, simulation and experimental results.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.1
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• pp.202-215
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• 2023

This paper proposes a non-orthogonal multiple access (NOMA) based low-complexity relaying approach for multiuser cellular two-way relay channels (CTWRCs). In the proposed scheme, the relay detects the signal using successive interference cancellation (SIC) and re-generates the transmit signal with zero-forcing (ZF) transmit precoding. The achievable data rates of the NOMA-based multiuser two-way relaying (TWR) approach is analyzed. We further study the power allocation among different data streams to maximize the weighted sum-rate (WSR). We re-form the resultant non-convex problem into a standard monotonic program. Then, we design a polyblock outer approximation algorithm to sovle the WSR problem.The proposed optimal power allocation algorithm converges fast and it is shown that the NOMA-TWR-OPA scheme outperforms a NOMA benchmark scheme and conventional TWR schemes.

• Structural Engineering and Mechanics
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• v.91 no.4
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• pp.403-416
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• 2024

The single-column pier girder bridge, due to its low engineering cost, small footprint, and aesthetic appearance, is extensively employed in urban viaducts and interchange ramps. However, its structural design makes it susceptible to eccentric loads, flexural-torsional coupling effects, and centrifugal forces, among others. To evaluate its anti-overturning performance reasonably, it is crucial to determine the reaction force of the support for the single-column pier girder bridge. However, due to the interaction between vehicle and bridge and the complexity of vibration modes, it poses a significant challenge to analyze the theory or finite element method of single-column pier girder bridges. The unit load bearing reaction coefficient method is proposed in this study to facilitate the static analysis. Numerous parameter analyses have been conducted to account for the dynamic amplification effect. The results of these analyses reveal that the dynamic amplification factor is independent of road surface roughness but is influenced by factors such as the position of the support. Based on parameter analysis, the formula of the dynamic amplification factor is derived by fitting.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.207-213
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• 2019

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.479-488
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• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.