• Transactions on Control, Automation and Systems Engineering
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• v.3 no.3
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• pp.181-189
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• 2001

The software components of embedded control systems get extremely complex as they are designed into distributed systems get extremely complex as they are designed into distributed systems consisting of a large number of inexpensive microcontrollers interconnected by low-bandwidth real-time networks such as the controller area network (CAN). While recently emerging middleware technologies such as CORBA and DCOM address the complexity of distributed programming, they cannot be directly applied to distributed control system design due to their excessive resource demand and inadequate communication models. In this paper, we propose a CORBA-based middleware design for CAN-based distributed embedded control systems. Our design goal is to minimize its resource need and make it support group communication without losing the IDL (interface definition language) level compliance to the OMG standards. To achieve this, we develop a transport protocol on the CAN and a group communication scheme based on the well-known publisher/subscriber model. The protocol effectively realizes subject-based addressing and supports anonymous publisher/subscriber communication. We also customize the method invocation and message passing protocol, referred to as the general inter-ORB protocol (GIOP), of CORBA so that CORBA method invocations are efficiently serviced on a low-bandwidth network such as the CAN. This customization includes packed data encoding and variable-length integer encoding for compact representation of IDL data types. We have implemented our CORBA-based middleware on the mArx real-time operating system we have developed at Seoul National University. Our experiments clearly demonstrate that it is feasible to use CORBA in developing distributed embedded control systems possessing severe resource limitations. Our design clearly demonstrates that it is feasible to use a CORBA-based middleware in developing distributed embedded systems on real-time networks possessing severe resource limitations.

• International Journal of Contents
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• v.14 no.3
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• pp.61-68
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• 2018

Unlike in the past, where the expression of the form was given a priority, with the widening of the scopes of the designs, the proportion of design education institution curricula targeting user experience and the application of technology is continually and gradually increasing. Open source microcontroller boards such as Arduino have initiated attracting attention as a countermeasure against these changes. These prototyping tools have many advantages for the diversification of expression and design verification in the design field and therefore have a high likelihood of being introduced into many design education institutes; however, the tools act as high entry barriers for design students who lack engineering knowledge. Although various educational content and tools have been developed to address the issue of barrier, existing solutions remain insufficient as alternatives for the purpose of activation. In this study, we investigated the present state of related education content and conducted a pilot workshop using a prototype microcontroller board with simplified coding. We intend to use the results of this investigation to develop study material for design education. We started by conducting a survey regarding the pre-university education situation. It was observed that engineering education opportunities are insufficient and the problem of mutual application between educations due to course-based education was not realized. We also analyzed the characteristics of simplified training tools using the microcontroller to establish a direction for educational design and conducted a pilot workshop using the microcontroller toolkit with a simplified coding process based on this content. Students who lack a basic knowledge of engineering technology received instruction, and after completing minimum preliminary training, they proceeded to practical exercises that involved utilizing the toolkit. Through this process, we identified the need for a simple-type microcontroller board with low-complexity for use in educating students majoring in design. We also identified some obstacles that serve as barriers to entry of utilizing microcontroller board. Based on these results, we propose several functional requirements and teaching guidelines for prototyping toolkits for design education.

• Structural Engineering and Mechanics
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• v.49 no.5
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• pp.631-644
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• 2014

Seismic assessment and retrofitting of existing structure is a complicated work that typically requires more sophisticated analyses than performing a new design. Before the implementation of a Code for seismic design of buildings (GBJ 11-89), not enough attention has been paid on seismic performance of structures and a great part of the existing reinforced concrete structures built in China have been poorly designed according to the new version of the same code (GB 50011-2010). This paper presents a case study of seismic assessment of a non-seismically designed reinforced concrete building in China. The structural responses are evaluated using the nonlinear static procedure (the so-called pushover analysis), which requires its introduction within a process that allows the estimation of the demand, against which the capacity is then compared with. The capacity of all structural members can be determined following the design code. Based on the structural performance, suitable retrofitting strategies are selected and implemented to the existing system. The retrofitted structure is analyzed again to check the effectiveness of the rehabilitation. Different types of retrofitting strategy are discussed and classified according to their complexity and benefits. Finally, a proper intervention methodology is utilized to upgrade this typical low-rise non-ductile building.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.3
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• pp.15-22
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• 2002

As the size and complexity of software systems increase, the design and specification of overall system structure become more significant issues than the choice of algorithms and data structures of computation. Software architecture serves as a framework for understanding system components and their interrelationships. Software architectures can be reusable assets to achieve low costs, high productivity, and consistent quality. We have developed a software architecture design environment, called Happy Work. In this paper, we would like to present the structure and functions of Happy Work. Happy Work has two main functions. First, it Provides a graphic editor for modeling of software architecture diagram. Second it provides an ADL, called HWL(Happy Work language). HWL is a language that describes software architect

• Journal of Power Electronics
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• v.17 no.5
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• pp.1231-1243
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• 2017

Grid-interactive power converters are normally synchronized with the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and the dc offsets in single-phase systems. In this paper, a single-phase PLL is presented to mitigate the effects of these non-idealities. This PLL is based on the popular second order generalized integrator (SOGI) structure. The SOGI structure is modified to eliminate the effects of input dc offsets. The resulting SOGI structure has a high-pass filtering property. Hence, this PLL is termed as a high-pass generalized integrator based PLL (HGI-PLL). It has fixed parameters which reduces the implementation complexity and aids in the implementation in low-end digital controllers. The HGI-PLL is shown to have the lowest resource utilization among the SOGI based PLLs with dc cancelling capability. Systematic design methods are evolved leading to a design that limits the unit vector THD to within 1% for given non-ideal input conditions in terms of frequency deviation and harmonic distortion. The proposed designs achieve the fastest transient response. The performance of this PLL has been verified experimentally. The results agree with the theoretical prediction.

• Journal of Information Processing Systems
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• v.15 no.3
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• pp.670-681
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• 2019

Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.34 no.9
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• pp.43-54
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• 2018

Recently, residents' community center is trying to combine with various program and facilities as the residents self-government program's development. This is due to the reduction of administrative tasks, the computerization of programs, the importance of community participation activities, the activation of community, and the increase of welfare projects. Therefore, previous studies on program complexity have been actively carried out. Nevertheless, spaces and programs studies of considering regional characteristics are lacking. Therefore, the community centers' program and spaces need to change. Therefore, this study propose an improvement direction through analyzing the situation of the residents' community center. For this study, the precedent research and institutional limitations are examined. In addition, this study selected and analyzed the 15 local community center. Thirdly, interviews were conducted with users and officials of the 5 residents' community centers on major changes. Finally, This study suggests direction of program improvement and architectural design direction. As a result of this study, integrated management measures with overlapping agencies should be sought. Surplus space will have to be rearranged into a new program through prior examination. Above all, the proposed remodeling guidelines require user requirements to be reflected and designed with the residents.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.56-62
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• 2008

Modern microprocessors must deliver high application performance, while the design process should not subordinate power. In terms of performance and power tradeoff, the instructions window is particularly important. This is because a large instruction window leads to achieve high performance. However, naive scaling conventional instruction window can severely affect the complexity and power consumption. This paper explores an architecture level approach to reduce power dissipation. We propose a low power issue logic with an efficient tag translation. The direct lookup table (DTL) issue logic eliminates the associative wake-up of conventional instruction window. The tag translation scheme deals with data dependencies and resource conflicts by using bit-vector based structure. Experimental results show that, for SPEC2000 benchmarks, the proposed design reduces power consumption by 24.45% on average over conventional approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.50-57
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and compared with the previous results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.34-42
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• 2012

Low density parity check (LDPC) code is widely used, since it shows superior performance close to Shannon limit and its decoding complexity is lower than turbo code. Recently, it is used as a channel code to decode Wyner-Ziv frames in distributed video coding (DVC) system. In this paper, we propose an efficient method to design the parity check matrix H of LDPC codes. In order to apply LDPC code to DVC system, the LDPC code should have rate compatibility. Thus, we also propose a method to merge check nodes of LDPC code to attain the rate compatibility. LDPC code is designed using ACE algorithm and check nodes are merged for a given code rate to maximize the error correction capability. The performance of the designed LDPC code is analyzed extensively by computer simulations.