• 제목/요약/키워드: low-complexity

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Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm

  • Park, Kyeongbin;Chung, Ki-Seok
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제15권2호
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    • pp.485-499
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    • 2021
  • Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

MB-OFDM UWB 통신 시스템을 위한 고속 2-Parallel Radix-$2^4$ FFT 프로세서의 설계 (A High-Speed 2-Parallel Radix-$2^4$ FFT Processor for MB-OFDM UWB Systems)

  • 이지성;이한호
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.533-534
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    • 2006
  • This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

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Low-Complexity Network Coding Algorithms for Energy Efficient Information Exchange

  • Wang, Yu;Henning, Ian D.
    • Journal of Communications and Networks
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    • 제10권4호
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    • pp.396-402
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    • 2008
  • The use of network coding in wireless networks has been proposed in the literature for energy efficient broadcast. However, the decoding complexity of existing algorithms is too high for low-complexity devices. In this work we formalize the all-to-all information exchange problem and shows how to optimize the transmission scheme in terms of energy efficiency. Furthermore, we prove by construction that there exists O(1) -complexity network coding algorithms for grid networks which can achieve such optimality. We also present low-complexity heuristics for random. topology networks. Simulation results show that network coding algorithms outperforms forwarding algorithms in most cases.

Low Complexity Vector Quantizer Design for LSP Parameters

  • Woo, Hong-Chae
    • The Journal of the Acoustical Society of Korea
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    • 제17권3E호
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    • pp.53-57
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    • 1998
  • Spectral information at a speech coder should be quantized with sufficient accuracy to keep perceptually transparent output speech. Spectral information at a low bit rate speech coder is usually transformed into corresponding line spectrum pair parameters and is often quantized with a vector quantization algorithm. As the vector quantization algorithm generally has high complexity in the optimal code vector searching routine, the complexity reduction in that routine is investigated using the ordering property of the line spectrum pair. When the proposed complexity reduction algorithm is applied to the well-known split vector quantization algorithm, the 46% complexity reduction is achieved in the distortion measure compu-tation.

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지역 복잡도 기반 방법 선택을 이용한 적응적 디인터레이싱 알고리듬 (Adaptive De-interlacing Algorithm using Method Selection based on Degree of Local Complexity)

  • 홍성민;박상준;정제창
    • 한국통신학회논문지
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    • 제36권4C호
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    • pp.217-225
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    • 2011
  • 본 논문에서는 영상의 지역 특성별로 보간 방법을 적응적으로 선택하여 적용하는 효과적인 디인터레이싱 알고리듬을 제안한다. 기존의 알고리듬들의 경우 각기 다른 방법으로 방향성을 구하기 때문에 영상의 지역 특성별로 성능이 다르게 나오는 경우가 있다. 또한, FDD(Fine Directional De-interlacing) 알고리듬의 경우 PSNR(Peak Signal-to-Noise Ratio)은 다른 알고리듬들에 비해 높게 나오지만 계산량이 많다는 단점이 있다. 이를 보안하기 위해 본 논문에서는 여러 영상들에서 계산량은 적으면서 화질 성능은 뛰어난 LA(Line Average), MELA(Modified Edge-based Line Average), LCID(Low-Complexity Interpolation Method for De-interlacing) 알고리듬들 중 지역복잡도 (DoLC, Degree of Local Complexity)별로 효과적인 알고리듬을 학습하여 이를 이용하여 보간을 수행하는 디인터레이싱 방법을 제안한다. 실험 결과 제안하는 방법은 좋은 성능에 비해 계산량이 적은 LCID 알고리듬과 비슷한 계산량을 보이면서 객관적 화질이 우수한 FDD, MELA 알고리듬보다 PSNR로 대표되는 객관적 화질과 주관적 화질 측면에서 우수한 결과를 나타내는 것을 알 수 있다.

비트-직렬 LDPC 복호를 위한 효율적 AT 복잡도를 가지는 두 최소값 생성기 (Efficient AT-Complexity Generator Finding First Two Minimum Values for Bit-Serial LDPC Decoding)

  • 이재학;선우명훈
    • 전자공학회논문지
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    • 제53권12호
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    • pp.42-49
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    • 2016
  • 논문은 저면적 비트-직렬 두 최소값 생성기를 제안한다. Min-sum 복호 알고리즘을 적용한 LDPC 복호기에서 두 최소값 생성기가 가장 큰 하드웨어 복잡도를 가지기 때문에, 두 최소값 생성기의 저면적 구현이 매우 중요하다. 하드웨어 면적을 줄이기 위해 비트-직렬 방식의 LDPC 복호기가 제안되었다. 하지만 기존의 비트-직렬 방식의 생성기는 하나의 최소값만 찾을 수 있어 BER 성능이 감소되었다. 제안하는 생성기는 두 최소값을 모두 찾을 수 있어 BER 성능열화를 극복하고 저면적의 LDPC 복호기 구현이 가능하다. 또한 기존의 두 최소값 생성기들과 비교하여 면적-시간 복잡도에서 가장 좋은 성능을 보인다.

Algorithm for Improving the Computing Power of Next Generation Wireless Receivers

  • Rizvi, Syed S.
    • Journal of Computing Science and Engineering
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    • 제6권4호
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    • pp.310-319
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    • 2012
  • Next generation wireless receivers demand low computational complexity algorithms with high computing power in order to perform fast signal detections and error estimations. Several signal detection and estimation algorithms have been proposed for next generation wireless receivers which are primarily designed to provide reasonable performance in terms of signal to noise ratio (SNR) and bit error rate (BER). However, none of them have been chosen for direct implementation as they offer high computational complexity with relatively lower computing power. This paper presents a low-complexity power-efficient algorithm that improves the computing power and provides relatively faster signal detection for next generation wireless multiuser receivers. Measurement results of the proposed algorithm are provided and the overall system performance is indicated by BER and the computational complexity. Finally, in order to verify the low-complexity of the proposed algorithm we also present a formal mathematical proof.

Low Complexity Decoder for Space-Time Turbo Codes

  • 이창우
    • 한국통신학회논문지
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    • 제31권4C호
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    • pp.303-309
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    • 2006
  • By combining the space-time diversity technique and iterative turbo codes, space-time turbo codes(STTCS) are able to provide powerful error correction capability. However, the multi-path transmission and iterative decoding structure of STTCS make the decoder very complex. In this paper, we propose a low complexity decoder, which can be used to decode STTCS as well as general iterative codes such as turbo codes. The efficient implementation of the backward recursion and the log-likelihood ratio(LLR) update in the proposed algorithm improves the computational efficiency. In addition, if we approximate the calculation of the joint LLR by using the approximate ratio(AR) algorithm, the computational complexity can be reduced even further. A complexity analysis and computer simulations over the Rayleigh fading channel show that the proposed algorithm necessitates less than 40% of the additions required by the conventional Max-Log-MAP algorithm, while providing the same overall performance.

Complexity-Reduced Algorithms for LDPC Decoder for DVB-S2 Systems

  • Choi, Eun-A;Jung, Ji-Won;Kim, Nae-Soo;Oh, Deock-Gil
    • ETRI Journal
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    • 제27권5호
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    • pp.639-642
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    • 2005
  • This paper proposes two kinds of complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.

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A Low-Complexity Planar Antenna Array for Wireless Communication Applications: Robust Source Localization in Impulsive Noise

  • Lee, Moon-Sik
    • ETRI Journal
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    • 제32권6호
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    • pp.837-842
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    • 2010
  • This paper proposes robust source localization methods for estimating the azimuth angle, elevation angle, velocity, and range using a low-complexity planar antenna array in impulsive non-Gaussian noise environments. The proposed robust source localization methods for wireless communication applications are based on nonlinear M-estimation provided from Huber and Hampel. Simulation results show the robustness performance of the proposed robust methods in impulsive non-Gaussian noise.