• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.40-46
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• 2005

A process variation compensation method called 'regulated drain detection' is proposed. This paper also shows the how this newly invented method is applied to a typical differential PLL. The proposed RDD(regulated drain detection) and its PLL application has been designed and tested in a $0.18{\mu}m$ 1-poly 3-metal plain digital process so that its stable performance and higher yield can be proven. The implemented PLL aimed to the operation range of 80MHz - 240MHz and the total die size is only $0.18{\mu}m$ including the internal loop filter. The tracking jitter characteristics is measured to less than 150 peak-to-peak under l.8V supply rail.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1C
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• pp.61-72
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• 2005

For the improvement of coding efficiency, the H.264 standard uses new coding tools such as VBS, 1/4-pel accurate ME, multiple references, intra prediction, loop filter, etc. Using these coding tools, H.264 has achieved significant improvements from rate-distortion point of view compared to existing standards. However, the encoder complexity is greatly increased due to these coding tools. We focus on the complexity reduction method of MB mode selection. Among all modes which can be selected, $8{\times}8$ and intra $4{\times}4$ mode have higher complexity than the others. So we propose the methods for reduction of the $8{\times}8$ and intra $4{\times}4$ mode complexity by using information of other modes with relatively low complexity. Simulation results show that the proposed methods save up to $54.6{\%}$ of total encoding time while keeping the average decrease about 0.012dB in PSNR.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.44-53
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• 2008

In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.6
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• pp.99-110
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• 2005

These days, many image processing techniques have been studied for effective image compression. Among those, The 2D image filtering is widely used for 2D image processing. The 2D image filtering can be implemented by performing the 1D linear filter separately in the horizontal and vertical direction. Efficiency of image compression depends on what filtering method is used. Generally, circular convolution is widely used in 2D image filtering for image processing. However it doesn't consider correlations at the boundary region of image, therefore effective filtering can not be performed. To solve this problem. I proposed new convolution technique using loop convolution which satisfies the 'alias-free' and 'error-free' requirement in the reconstructed image. This method could provide more effective compression performance than former methods because it used highly-correlated data when performed at the boundary region. In this paper, Sub-band Coding(SBC) was adopted to analyze efficiency of proposed filtering technique, and the simulator developed by Java-based language was used to examine the performance of proposed method.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.9-17
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• 2000

In this paper we implement computer simulation system of 4FSK signal MODEM using Quadrature detector and analyze overall tranceiver system. We follow the FLEX wireless paging system standards and construct premodulation filter and data frame. We propose an efficient open loop symbol timing recovery algorithm which takes advantage of 128 bit length preamble pattern and also propose a 32 bit UW pattern which Is based on the optimal UW detection method, and excellent aperiodic autocorrelation characteristic. The BER simulation in the fading channel as well as AWGN is performed with BCH coding and Interleaving to the Quadrature detector system and it is shown that a high coding fain occurs in the fading channel rather than AWGN channel.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.1
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• pp.63-68
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• 2004

In this paper, we propose a method about the extraction of vehicle and tracking trajectory for moving vehicle tracking system in road. This system applied to the monitoring system of the traffic flow for ATMS(advanced traffic management system) of ITS(intelligent transport system). Also, this system can solve the problem of maintenance of loop sensor. And we detected vehicle using differential image analysis. Because of the road environment changes by real time. Therefore, the method to use background image is not suitable. And we used Kalman filter and innovation value and variable search area for vehicle tracking system. Previous method using fixed search area is sensitive to the moving trajectory and the speed of vehicle. Simulation results show that proposed method increases the possibility of traffic measurement more than fixed area traffic measurement system.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.11a
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• pp.387-390
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• 2005

A This paper presents a novel three-phase current-fed Pulse Width Modulation converter with switched- capacitor type resonant DC link commutation circuit operating PWM pattern strategy under a design consideration of low-pass filter, which can operate on the basis of the principle of zero current soft-switching commutation. In the first place, the steady-state operating principle of this converter with a new resonant DC link snubber circuit is described in connection with the equivalent operation circuit, together with the practical design procedure of the switched-capacitor type resonant DC link circuit is discussed from a theoretical viewpoint on the basis of a design example for high-power applications. The actively delayed time correction method to compensate distorted currents due to a relatively long resonant commutation time is newly implemented in the open loop control scheme so as to acquire the new optimum PWM pattern. Finally, the experiment or set-up in laboratory system or this converter is concretely demonstrated herein to confirm a zero current soft-switching commutation of this converter. The comparative evaluations between current-fed hard switching PWM and soft-switching PWM converters are carried out from a viewpoint of their PWM converter characteristics.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.4
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• pp.309-316
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• 2011

A PLL system has widely used for synchronizing the grid voltage at the grid-connected inverter for supplying power from the PV generation systems. In this paper, a PLL algorithm without both the loop filter and PI controller is suggested for improving the performance of synchronization at the single-phase and three-phase grid connected inverters. In order that the output voltage of a phase detector in the PLL has only a dc voltage, and it approaches to 0 when the synchronization signal is locked to the grid voltage, the feedback signals are determined by using two-phase voltages. After the PLL system with a proportional controller is modelled with the small signal analysis, the stability and steady-state error are investigated. Through the simulation studies and experimental results, the performances of the proposed PLL algorithm are verified.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.531-537
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• 2018

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1776-1782
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• 2010

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability (0.22deg) and scale factor stability, extremely low angle random walk (0.07deg) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The Cascaded integrator bomb(CIC) type of decimation filter only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.