• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.5
• /
• pp.77-86
• /
• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Korean Journal of Materials Research
• /
• v.30 no.10
• /
• pp.495-501
• /
• 2020

The various sintered samples comprising of 72 wt% (Al₂O₃) : 28 wt% (SiO₂) based ceramics were fabricated using a colloidal processing route. The phase analysis of the ceramics was performed using an X-ray diffractometer (XRD) at room temperature confirming the presence of Al₂O₅Si and Al_5.33Si_0.67O_9.33. The surface morphology of the fracture surface of the different sintered samples having different sizes of grain distribution. The resistive and capacitive properties of the three different sintered samples at frequency sweep (1 kHz to 1 MHz). The contribution of grain and the non-Debye relaxation process is seen for various sintered samples in the Nyquist plot. The ferroelectric loop of the various sintered sample shows a slim shape giving rise to low remnant polarization. The excitation performance of the sample at a constant electric signal has been examined utilizing a designed electrical circuit. The above result suggests that the prepared lead-free ceramic can act as a base for designing of dielectric capacitors or resonators.

• Journal of Power Electronics
• /
• v.13 no.4
• /
• pp.516-527
• /
• 2013

This paper presents a new overall system for state-of-available-power (SoAP) prediction for a lithium-ion battery pack. The essential part of this method is based on an adaptive network architecture which utilizes both fuzzy model (FIS) and artificial neural network (ANN) into the framework of adaptive neuro-fuzzy inference system (ANFIS). While battery aging proceeds, the system is capable of delivering accurate power prediction not only for room temperature, but also at lower temperatures at which power prediction is most challenging. Due to design property of ANN, the network parameters are adapted on-line to the current battery states (state-of-charge (SoC), state-of-health (SoH), temperature). SoC is required as an input parameter to SoAP module and high accuracy is crucial for a reliable on-line adaptation. Therefore, a reasonable way to determine the battery state variables is proposed applying a combination of several partly different algorithms. Among other SoC boundary estimation methods, robust extended Kalman filter (REKF) for recalibration of amp hour counters was implemented. ANFIS then achieves the SoAP estimation by means of time forward voltage prognosis (TFVP) before a power pulse occurs. The trade-off between computational cost of batch-learning and accuracy during on-line adaptation was optimized resulting in a real-time system with TFVP absolute error less than 1%. The verification was performed on a software-in-the-loop test bench setup using a 53 Ah lithium-ion cell.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.8C
• /
• pp.790-800
• /
• 2009

For the improvement of coding efficiency, the H.264/AYC standard uses new coding tools such as 1/4-pel-accurate motion estimation, multiple references, intra prediction, loop filter, variable block size etc. Using these coding tools, H.264/AYC has achieved significant improvements from rate-distortion point of view compared to existing standards. However, the encoder complexity was greatly increased due to these coding tools. We focus on the complexity reduction method of intra macroblock mode selection. The proposed algorithm for fast intra mode selection calculates the edge activity in transform domain, and performs fast encoding of intra frame in H.264/AYC through the fast prediction mode selection of intra4x4 and chrominance blocks. Simulation results show that the proposed method saves about 59.76% for QCIF sequences and 65.03% for CIF sequences of total encoding time, while bitrate increase and PSNR decrease are very small.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.1B
• /
• pp.183-192
• /
• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.7A
• /
• pp.1028-1035
• /
• 1999

To increase the throughput of data transmission in burst-mode TDMA communication systems and also to get a good BER performance at the same time, it is essential to rapidly acquire the carrier while keeping the desirable tracking performance. To achieve this goal, in this paper, a new decision-directed carrier recovery algorithm is presented. The proposed scheme does not incorporate the PLL and suppress the Gaussian random process of input noise by the pre-stage low pass filter so as to get both the fast acquisition and a good performance. Through computer simulations, the performance of the scheme is analyzed with respect to the acquisition time and bit error rate. The cycle slip in the proposed scheme is seldom observed at very low SNR environment in contrast to the previous proposed one. Because of this merit, it is not required to do the differential encoding and decoding in the proposed scheme.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.6C
• /
• pp.637-644
• /
• 2006

This paper presents performance and implementation comparisons of standard and fast DCT algorithms that are commonly used for subband filter bank in MPEG audio coders. The comparison is made according to the architectural difference of the implementation hardware. Fast DCT algorithms are known to have much less computational complexity than the standard method that involves computing a vector dot product of cosine coefficient. But, due to structural irregularity, fast DCT algorithms require extra cycles to generate the addresses for operands and to realign interim data. When algorithms are implemented using DSP processors that provide special operations such as single-cycle MAC (multiply-accumulate), zero-overhead nested loop, the standard algorithm is more advantageous than the fast algorithms. Also, in case of the finite-precision processing, the error performance of the standard method is far superior to that of the fast algorithms. In this paper, truncation errors and algorithmic suitability are analyzed and implementation results are provided to support the analysis.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.14 no.8
• /
• pp.809-815
• /
• 2003

It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.

• Proceedings of the KIPE Conference
• /
• 2008.06a
• /
• pp.103-105
• /
• 2008

In grid-interconnection system, a fast, robust and precise phase angle detector is most important to grid synchronization and the active power control. The phase angle can be easily estimated by synchronous dq PLL system. On the other hand under unbalanced voltage condition, synchronous dq PLL system has problem that harmonics occur to phase angle or magnitude of grid voltage because of the effect of the negative sequence components. So, To eliminate the negative sequence components, the PLL method using APF (All Pass Filter) in a stationery reference frame to extract positive sequence components under unbalanced voltage condition is researched. In this paper, we propose a new PLL method with decoupling network using APF in a synchronous reference frame to extract the positive sequence components of the grid voltage under unbalanced grid. The cut-off frequency of APF in a synchronous reference frame can be set to twice of the fundamental frequency comparing with that of APF in a stationery reference frame which is the fundamental frequency. The proposed PLL strategy can detect the phase angle quickly and accurately under unbalanced gird voltages. Simulation and experimental results are presented to verify the proposed strategy under different kind of voltage dips.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.24 no.6
• /
• pp.609-614
• /
• 2014

Cerebellar ataxia is a steadily progressive neurodegenerative disease associated with loss of motor control, leaving patients unable to walk, talk, or perform activities of daily living. Direct motor instruction in cerebella ataxia patients has limited effectiveness, presumably because an inappropriate closed-loop cerebellar response to the inevitable observed error confounds motor learning mechanisms. Recent studies have validated the age-old technique of employing motor imagery training (mental rehearsal of a movement) to boost motor performance in athletes, much as a champion downhill skier visualizes the course prior to embarking on a run. Could the use of EEG based BCI provide advanced biofeedback to improve motor imagery and provide a "backdoor" to improving motor performance in ataxia patients? In order to determine the feasibility of using EEG-based BCI control in this population, we compare the ability to modulate mu-band power (8-12 Hz) by performing a cued motor imagery task in an ataxia patient and healthy control.