• Title/Summary/Keyword: look up table

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A Study on Real Time Color Gamut Mapping Using Tetrahedral Interpolation (사면체 보간을 이용한 실시간 색역 사상에 관한 연구)

  • Kim, Kyoung-Seok;Kwon, Do-Hyung;Lee, Hak-Sung;Han, Dong-Il
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.1
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    • pp.56-63
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    • 2007
  • A color gamut mapping has been known to be one of promising methods to enhance display quality of various types of color display device. However, it is required to handle this mapping in real time for display or digital TV application. If carefully arranged, the tetrahedral interpolation can be computed with simpler operations compared to a cubic interpolation in the conventional reduced resolution look-up table which is devised to process the gamut mapping in real time. Based on the tetrahedral interpolation, a new type hardware architecture for real-time gamut mapping is proposed in this paper. The proposed hardware architecture shows better processing speed and reduces the hardware cost.

A Design of DisplayPort AUX Channel (디스플레이포트 인터페이스의 AUX 채널 설계)

  • Cha, Seong-Bok;Yoon, Kwang-Hee;Kim, Tae-Ho;Kang, Jin-Ku
    • Journal of IKEEE
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    • v.14 no.1
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    • pp.1-7
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    • 2010
  • This paper presents an implementation of the DisplayPort AUX(Auxiliary) Channel. DisplayPort uses Main link, AUX Channel and Hot Plug Detect line to transfer the video & audio data. For isochronous transport service, source device converts to image and audio data which are to be transported through the Main Link and transports the restructured image and audio data to sink device. The AUX Channel provides link service and device service for discovering, initializing and maintaining the Main link. Hot Plug Detect line is used to confirm the connection between source device and sink device. The AUX Channel is implemented with 3315 LUTs(Look Up Table), 1466 Flip Flops and 168.782MHz max speed synthesized using Xilinx ISE 9.2i at SoC Master3.

An Off-line Maximum Torque Control Strategy of Wound Rotor Synchronous Machine with Nonlinear Parameters

  • Wang, Qi;Lee, Heon-Hyeong;Park, Hong-Joo;Kim, Sung-Il;Lee, Geun-Ho
    • Journal of Electrical Engineering and Technology
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    • v.11 no.3
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    • pp.609-617
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    • 2016
  • Belt-driven Starter Generator (BSG) differs from other mild hybrid systems as the crankshaft of vehicle are not run off. Motor permits a low-cost method of adding mild hybrid capabilities such as start-stop, power assist, and mild levels of regenerative braking. Wound rotor synchronous motor (WRSM) could be adopted in BSG system for HEV e-Assisted application instead of the interior permanent magnet synchronous motor (IPMSM). In practice, adequate torque is indispensable for starter assist system, and energy conversion should be taken into account for the HEV or EV as well. Particularly, flux weakening control is possible to realize by adjusting both direct axis components of current and field current in WRSM. Accordingly, this paper present an off-line current acquisition algorithm that can reasonably combine the stator and field current to acquire the maximum torque, meanwhile the energy conversion is taken into consideration by losses. Besides, on account of inductance influence by non-uniform air gap around rotor, nonlinear inductances and armature flux linkage against current variation are proposed to guarantee the results closer to reality. A computer-aided method for proposed algorithm are present and results are given in form of the Look-up table (LUT). The experiment shows the validity of algorithm.

A Study on Establishment of the Standard Size for High School Girls -The Girls of Seventeen Years Old in Seoul- (여고생의 의복치수 설정을 위한 연구 -주로 서울시내 17세 여고생을 중심으로-)

  • Son Won Kyo
    • Journal of the Korean Society of Clothing and Textiles
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    • v.1 no.1
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    • pp.1-5
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    • 1977
  • 'Adolescence' is a critical period in the process of growing and aging but important in that an adolescent becomes aware of and begins to look about him or her self. Especially with girls in their late teens (15$\~$18), they pay more attention to their looks and clothes than the boys do, which affects to some extent the formation of their personality and their behavior. From this point .of view. it is significant to establish the standard size of high-school girls' clothes. This study aims to measure high-school girls in size and to establish the standard size of their clothes; furthermore. to enable them to lead a satisfactory living with more appropriate size of clothes. The results, analyzed by two different representing items which resulted in little difference, are as belows: 1) Stature had a significant correlation with posterior waist height; bust girth had the most significant correlation with weight. and also some considerable correlation with other representing items; 2) The F-test result showed significant difference on $1\%$ level over all the items between the measured (Y) and the estimated (Y); the correlation among the representing items was considerable also; 3) When the measurement increases in stature by 4cm, bust girth by 4cm. and posterior shoulder width by 2cm respectively, the increase or decrease in other items are as shown on Table 4. Since this study was carried out in girls' high-schools in Seoul, it is expected to extend its further study throughout the nation. thus contributing to comprehending the whole truth of people's body-size and promoting the fabrication and modelling of the original clothes for the nation by the strict standard size up to making ready-made clothes with no difficulty in setting the standard and model size.

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A FPGA Design of High Speed LDPC Decoder Based on HSS (HSS 기반의 고속 LDPC 복호기 FPGA 설계)

  • Kim, Min-Hyuk;Park, Tae-Doo;Jung, Ji-Won
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.11
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    • pp.1248-1255
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    • 2012
  • LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

Forward Vehicle Movement Estimation Algorithm (전방 차량 움직임 추정 알고리즘)

  • Park, Han-dong;Oh, Jeong-su
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.9
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    • pp.1697-1702
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    • 2017
  • This paper proposes a forward vehicle movement estimation algorithm for the image-based forward collision warning. The road region in the acquired image is designated as a region of interest (ROI) and a distance look up table (LUT) is made in advance. The distance LUT shows horizontal and vertical real distances from a reference pixel as a test vehicle position to any pixel as a position of a vehicle on the ROI. The proposed algorithm detects vehicles in the ROI, assigns labels to them, and saves their distance information using the distance LUT. And then the proposed algorithm estimates the vehicle movements such as approach distance, side-approaching and front-approaching velocities using distance changes between frames. In forward vehicle movement estimation test using road driving videos, the proposed algorithm makes the valid estimation of average 98.7%, 95.9%, 94.3% in the vehicle movements, respectively.

Implementation of the high speed signal processing hardware system for Color Line Scan Camera (Color Line Scan Camera를 위한 고속 신호처리 하드웨어 시스템 구현)

  • Park, Se-hyun;Geum, Young-wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.9
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    • pp.1681-1688
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    • 2017
  • In this paper, we implemented a high-speed signal processing hardware system for Color Line Scan Camera using FPGA and Nor-Flash. The existing hardware system mainly processed by high-speed DSP based on software and it was a method of detecting defects mainly by RGB individual logic, however we suggested defect detection hardware using RGB-HSL hardware converter, FIFO, HSL Full-Color Defect Decoder and Image Frame Buffer. The defect detection hardware is composed of hardware look-up table in converting RGB to HSL and 4K HSL Full-Color Defect Decoder with high resolution. In addition, we included an image frame for comprehensive image processing based on two dimensional image by line data accumulation instead of local image processing based on line data. As a result, we can apply the implemented system to the grain sorting machine for the sorting of peanuts effectively.

Hardware Design of SNR Estimator for Adaptive Satellite Transmission System (적응형 위성 전송 시스템을 위한 신호 대 잡음비 추정 회로 구현)

  • Lee, Jae-Ung;Kim, Soo-Seong;Park, Eun-Woo;Im, Chae-Yong;Yeo, Sung-Moon;Kim, Soo-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.2A
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    • pp.148-158
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    • 2008
  • This paper proposes an efficient signal to noise ratio (SNR) estimation algorithm and its hardware implementation for adaptive transmission system using M-ary modulation scheme. In this paper, we present the implementation results of the proposed algorithm for the second generation digital video broadcasting via satellite (DVB-S2) system, and the proposed algorithm can be tailored to the other communication systems using adaptive transmissions. We built a look-up table (LUT) using the theoretical background of the received signal distribution, and by using this LUT we need just two comparators and a counter for the hardware implementation. For this reason, the hardware of the proposed scheme produces accurate estimation results even with extremely low complexity. The simulation results investigated in this paper reveal that the proposed method can produce estimation results within the specified SNR range in the DVB-S2 system, and it requires a few hundreds of samples for average estimation error of about 1 dB.

DOF Correction of Heterogeneous Stereoscopic Cameras (이종 입체영상 카메라의 피사계심도 일치화)

  • Choi, Sung-In;Park, Soon-Yong
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.7
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    • pp.169-179
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    • 2014
  • In this paper, we propose a DOF (Depth of Field) correction technique by determining the values of the internal parameters of a 3-D camera which consists of stereoscopic cameras of different optical properties. If there is any difference in the size or the depth range of focused objects in the left and right stereoscopic images, it could cause visual fatigue to human viewers. The object size of in the stereoscopic image is corrected by the LUT of zoom lenses, and the forward and backward DOF are corrected by the object distance. Then the F-numbers are determined to adjust the optical properties of the camera for DOF correction. By applying the proposed technique to a main-sub type 3-D camera using a GUI-based DOF simulator, the DOF of the camera is automatically corrected.

A Hardware Design for Realtime Correction of a Barrel Distortion Using the Nearest Pixels on a Corrected Image (보정 이미지의 최 근접 좌표를 이용한 실시간 방사 왜곡 보정 하드웨어 설계)

  • Song, Namhun;Yi, Joonhwan
    • Journal of the Korea Society of Computer and Information
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    • v.17 no.12
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    • pp.49-60
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    • 2012
  • In this paper, we propose a hardware design for correction of barrel distortion using the nearest coordinates in the corrected image. Because it applies the nearest distance on corrected image rather than adjacent distance on distorted image, the picture quality is improved by the image whole area, solve the staircase phenomenon in the exterior area. But, because of additional arithmetic operation using design of bilinear interpolation, required arithmetic operation is increased. Look up table(LUT) structure is proposed in order to solve this, coordinate rotation digital computer(CORDIC) algorithm is applied. The results of the synthesis using Design compiler, the design of implementing all processes of the interpolation method with the hardware is higher than the previous design about the throughput, In case of the rear camera, the design of using LUT and hardware together can reduce the size than the design of implementing all processes with the hardware.