• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.5
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• pp.62-70
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• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.10
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• pp.928-936
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• 2013

3D crosstalk is one of the disturbing things to recognize 3D images. This is caused by the phenomenon that input image for left eye is transferred at the right eye and right eye is transferred at the left eye because of the imperfect isolation by the device characteristics. In this paper, we review the 3D PDP (Plasma Display Panel) operation using active shutter glasses and crosstalk measurement method and investigate the major cause of 3D crosstalk and extend conventional 3D crosstalk using full white and full black image input to Gray-to-Gray (GtoG) 3D crosstalk. We suggest a specific method to reduce Gray-to-Gray 3D crosstalk by using Look up Table (LUT) and sub-field mapping in PDP. And then, we verify the method by measuring GtoG 3D crosstalk rate through specific test images and numerical results.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1235-1238
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• 2004

Thresholding has been used to reduce the number of gray values in images. Typically, a single threshold value has been used, resulting in two gray level images. Image reduction of one single threshold value, however, may lose too much of the high-frequency edge information. Thus, dynamic thresholding that uses a different threshold for each pixel is preferred instead of using a single threshold value. Dynamic thresholding can preserve high frequency details as well as reduce the size of images. Since it takes long time to perform existing software dynamic thresholding in an embedded system, this paper proposes and implements a circuit by using a FPGA in order to perform a real-time dynamic thresholding,. The proposed circuit consists of two counters, and threshold look-up table, and control unit. The values of two counters determine each pixel position, the threshold look-up table converts each pixel value into other value, and the control unit generates necessary control signals. On arriving from a camera to the proposed circuit, each pixel is compared with its threshold value and is converted into other gray value. An image processing system by using the proposed circuit will be implemented and some experiments will be performed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.53-60
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• 2009

A low-power/small-area 128-point FFT processor is designed, which is based on logarithmic number system (LNS) and some design techniques to minimize both hardware complexity and arithmetic error. The complex-number multiplications and additions/subtractions for FFT computation are implemented with LNS adders and look-up table (LUT) rather than using conventional two's complement multipliers and adders. Our design reduces the gate counts by 21% and the memory size by 16% when compared to the conventional two's complement implementation. Also, the estimated power consumption is reduced by about 18%. The LNS-based FFT processor synthesized with 0.35 ${\mu}m$ CMOS standard cell library has 39,910 gates and 2,880 bits memory. It can compute a 128-point FIT in 2.13 ${\mu}s$ with 60 MHz@2.5V, and has the average SQNR of 40.7 dB.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.131-144
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• 2015

An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.262-263
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• 2008

LCD 디바이스는 그 동작원리와 전기-광학적 특성에 의해 CRT와는 다른 감마곡선 특성을 갖고 있다. 대부분의 LCD디스플레이 디바이스들의 감마곡선은 CRT와는 달리 일관성을 갖지 않을 뿐 더러 흑백계조입력을 기준으로 하는 감마보정을 위해 RED, GREEN, BLUE 입력값을 세부적으로 조정할 때 각 계조입력에 대한 상관색온도가 일정한 값을 갖지 않아 LCD의 특성에 대한 모델링과 보정에 어려움이 있다. 또한, 애플사의 맥머신 그리고 실리콘 그래픽스사의 시스템과 같이 소정의 감마값을 전제로 해당 시스템의 내부참조테이블(internal look-up table)이 설계되어 각기 다른 시스템감마를 가지는 장치들에 의해 인코딩되어진 영상출력신호의 경우, 동일한 시스템을 갖추거나 시스템감마에 대한 역감마특성을 가진 디스플레이장치가 아닌 환경에서는 원본영상에 대한 왜곡은 더욱 커질 수 있다. 특히, 낮은 흑백계조입력에서의 색온도의 경우, 파장에 따라 서로 다른 감쇄성능을 가진 일반적인 컬러필터의 특성에 의한 누설광(light leakage)에 의해 결정되며, 이로 인해 색온도가 특정한 객을 띄는 현상이 발생한다. 본 논문에서는 LCD디스플레이의 감마곡선을 여러 가지 시스템감마에 대응할 수 있는 감마곡선예 일치시키고, 계조선형성을 동시에 개선하기 위하여 입력 디지털값과 삼자극치간 관계를 나타내는 여러 가지 컬러모델링 방법 중에서 PLCC(Piecewise Linear Interpolation assuming Constant Chromaticity coordinates)모델을 적용하고, 목표로 하는 감마곡선과 색온도를 만족하기 위한 새로운 입력값을 구한 후 이를 컬러참조테이블(color look-up table)예 적용하는 방법과 저계조에서의 색온도를 목표색온도에 근접시키는 방법을 제안한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.6
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• pp.602-611
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• 2004

Servo system has commonly adapted PI controller with fixed gains, because of its simplicity and determinative relationship among the parameters. The fixed gains PI system may be applied well to some operation conditions, but not non-linearities, complex and time variant operation conditions. For solving these problems, another conventional method, 'variable gun schedule according to speed', is published. The value of gain is determined according to the absolute value of the mover real speed. In this paper, FSTPIC(Fuzzy Self-Tuning PI Controller) is proposed based on various experiences to rapidly reduce speed error and to secure a good speed response characteristics. The effectiveness of proposed algorithms is demonstrated by comparing to two conventional gain systems via 4-quadrant operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.