• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.3 no.1
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• pp.44-51
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• 2003

Knowledge acquisition is a bottleneck in knowledge-based system implementation. Decision tree induction is a useful machine learning approach for extracting classification knowledge from a set of training examples. Many real-world data contain fuzziness due to observation error, uncertainty, subjective judgement, and so on. To cope with this problem of real-world data, there have been some works on fuzzy classification rule learning. This paper makes a survey for the kinds of fuzzy classification rules. In addition, it presents a fuzzy classification rule learning method based on decision tree induction, and shows some experiment results for the method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.491-499
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• 2007

In this paper, we present a design method of the ternary logic circuits based on Reed-Muller expansions. The design method of the presented ternary logic circuits checks the degree of each variable for the coefficients of Reed-Holler Expansions(RME) and determines the order of optimal control input variables that minimize the number of Reed-Muller Expansions modules. The order of optimal control input variables is utilized the computation of circuit cost matrix. The ternary logic circuits of the minimized tree structures to be constructed by RME modules based on Reed-Muller Expansions are realized using the computation results of its circuit cost matrix. This method is only performed under unit time in order to search for the optimal control input variables. Also, this method is able to be programmed by computer and the run time on programming is $3^n$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.711-718
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• 2019

BDD is a well-known alternative to the conventional Boolean logic method in fault tree analysis. As the size of fault tree increases, the calculation time and computer resources for BDD dramatically increase. A new failure path search and path restructure method is proposed for efficient calculation of CS and MCS from BDD. Failure path grouping and bottom-up path search is proved to be efficient in failure path search in BDD and path restructure is also proved to be used in order to reduce the number of CS comparisons for MCS extraction. With these newly proposed methods, the top event probability can be calculated using the probability by ASDMP(Approximate Sum of Disjoint MCS Products), which is shown to be equivalent to the result by the conventional MCUB(Minimal Cut Upper Bound) probability.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.4
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• pp.328-333
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• 2013

Since a slight malfunction of control systems in a nuclear power plant may cause huge catastrophes, such control systems usually have multiple redundancy and reliable features, and their reliability and availability should be analyzed and verified thoroughly. This paper performed the reliability analysis of the SPLC (Safety Programmable Logic Controller) that is under developed as the control systems for the next generation nuclear power plant. One of the key features of SPLC is that it has multiple redundancy modes as faults happen, which means the reliability analysis for one fixed redundant model is not enough to analyze the reliability of SPLC. With considering this reconfigurable concept, FTA (Fault Tree Analysis) was used to capture fault-relationship among sub-modules. The analysis results show that MTTF (Mean Time to Fault) of SPLC is 45,080 hours, which is a about 4.5 times longer than the regulation, 10,000 hours.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.1285-1293
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• 2008

Locking sheet is to display the contents of interlocking equipment for safe train drive in stations. It is being used as a basic information for interlocking equipment and for route control condition and the discussion for train operation between related parties. In spite of importance of this, there was no other way except depending on the work by hands from each stage(drawing, examination, discussion, approval) due to non-existing any tool. It is written it takes 30days from drawing to approval by procedures. However, it is required over the days in real time due to argument of each party. Furthermore on drawing of locking sheet, special conditions applied in accordance with situations of each station occasionally are different depending on the person in charge. Therefore, it is urgent to make up Logic Tree to accept special conditions of all stations. Automation Program for Drawing and Examination of Locking Sheet is to improve inefficient interlocking operation which was operated by hands in accordance with custom as automated system. The target of this program is to minimize the processing time and potential errors by personal work and set up standards for Logic Tree of special condition.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.8
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• pp.2042-2060
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• 2013

In wireless sensor networks (WSNs), energy efficiency is one of the most essential design considerations, since sensor nodes are resource constrained. Group communication can reduce WSNs communication overhead by sending a message to multiple nodes in one packet. In this paper, in order to simultaneously resolve the transmission security and scalability in WSNs group communications, we propose a hierarchical cluster-based secure and scalable group key management scheme, called HRKT, based on logic key tree and route key tree structure. The HRKT scheme divides the group key into cluster head key and cluster key. The cluster head generates a route key tree according to the route topology of the cluster. This hierarchical key structure facilitates local secure communications taking advantage of the fact that the nodes at a contiguous place usually communicate with each other more frequently. In HRKT scheme, the key updates are confined in a cluster, so the cost of the key updates is reduced efficiently, especially in the case of massive membership changes. The security analysis shows that the HRKT scheme meets the requirements of group communication. In addition, performance simulation results also demonstrate its efficiency in terms of low storage and flexibility when membership changes massively.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.1
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• pp.20-25
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• 2002

This paper presents a genetic programming based evolutionary strategy for on-line adaptive learnable evolvable hardware. Genetic programming can be useful control method for evolvable hardware for its unique tree structured chromosome. However it is difficult to represent tree structured chromosome on hardware, and it is difficult to use crossover operator on hardware. Therefore, genetic programming is not so popular as genetic algorithms in evolvable hardware community in spite of its possible strength. We propose a chromosome representation methods and a hardware implementation method that can be helpful to this situation. Our method uses context switchable identical block structure to implement genetic tree on evolvable hardware. We composed an evolutionary strategy for evolvable hardware by combining proposed method with other's striking research results. Proposed method is applied to the autonomous mobile robots cooperation problem to verify its usefulness.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.8
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• pp.1057-1063
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• 1995

This paper describes an approach for constucting a Rectilinear Steiner Tree (RST) derivable from a Minimum Spanning Tree (MST), using Associative Processor (AP). We propose a fast parallel algorithm using AP's basic algorithms which can be realized by the processing capability of rudimentary logic and the selective matching capability of Content- Addressable Memory (CAM). The main idea behind the proposed algorithm is to maximize the overlaps between the consecutive edges in MST, thus minimizing the cost of a RST. An efficient parallel linear algorithm with O(n) complexity to construct a RST is proposed using an algorithm to find a MST, where n is the number of nodes. A node insertion method is introduced to allow the Z-type layout. The routing process which only depends on the neighbor edges and the no-rerouting strategy both help to speed up finding a RST.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.3
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• pp.194-197
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• 2002

This paper considers the problem of routing connections in a optical multi tree networks using WDM (Wavelength Division Multiplexing), where each connection between a pair of nodes in the network is assigned a path through the network and a wavelength on that path, so that connections whose paths share a common link in the network are assigned different wavelengths. The problem of optimal coloring of the paths on the optical multi-networks is NP-hard[1], but if that is the coloring of all paths, then there exists efficient polynomial time algorithm. In this paper, using a "divide & conquer" method, we give efficient algorithm to assign wavelengths to all the paths of a tree network based on the theory of [7]. Here, our time complexity is 0(n4log n).