• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.31-34
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• 1995

The automated chemical analysis shop floor are developed for the environmental pollution problems in our chemical analysis center. This shop floor have the several equipments include weight, pour, dry, heater, boiler, mixture, spectroscopy etc. And the material handling components are made up by the stored stack, conveyore, turntables, robot etc. Computer simulation has been an important tool for these complete design problem. We have designed the arangement of chemical equipments and material flow systems by using the simulator "AutoModII". "AutoMoII" is one of the advanced simulator, CAD-like drawing tools with a powerful, engineering oriented language to model control logic and material flow. The result is the modeling of the chemical analysis system in accurate, three dimensional detail. We could designed the set able layout and scheduling system by using the AutoMoII simulator. AutoMoII simulator.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.309-312
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• 2001

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1787-1790
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• 2003

In this paper. we proposed a hardware(H/W) structure which can compress the video and embed the watermark in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. The global operations of the designed H/W consists of the image compression with the watermarking and the reconstruction, and the watermarking operation is concurrently operated with the image compression. The implemented H/W used the 59％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency over. So we verified the real time operation, 60 fields/sec(30 frames/sec).

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.152-161
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• 1996

This paper descrisbes the implementation of a 20D DCT that can be used for video conference, JPEG, and MPEG-related applications. The implemented DCT consists of two 1-D DCTs and a transposed memory between them, and uses ROM-based multipliers instead of conventional ones. As the system bit length, the minimum bit length that satisfies the accuracy specified by the ITU standard H.261 was chosen through the simulations using the C language. The proposed design uses a dual port RAM for the transposed memory, and processes two bits of input-pixel data simultaneously t ospeed up addition process using two sets of ROMs. The basic system architecture was designed using th Synopsys schematic editor, and internal modules were described in VHDL and synthesized to logic level after simulation. Then, the compass silicon compiler was used to create the final lyout with 0.8um CMOS libraries, using the standard cell approach. The final layout contains about 110, 000 transistors and has a die area of 4.68mm * 4.96mm, and the system has the processing speed of about 50M pixels/sec.

• Journal of Computing Science and Engineering
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• v.5 no.1
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• pp.85-110
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• 2011

Achieving situation awareness is especially challenging for real-time data stream applications because they i) operate on continuous unbounded streams of data, and ii) have inherent realtime requirements. In this paper we showed how formal data stream modeling and analysis can be used to better understand stream behavior, evaluate query costs, and improve application performance. We used MEDAL, a formal specification language based on Petri nets, to model the data stream queries and the quality-of-service management mechanisms of RT-STREAM, a prototype system for data stream management. MEDAL's ability to combine query logic and data admission control in one model allows us to design a single comprehensive model of the system. This model can be used to perform a large set of analyses to help improve the application's performance and quality of service.

• Journal of Sensor Science and Technology
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• v.21 no.1
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• pp.21-27
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• 2012

In this study, we designed an embedded system for automatic condensation control(ESCC) of the car. This system heats the car glasses as and when it is needed that makes driving safer and convenient. The system was built on an ATmega128L central processing unit(CPU), using high-performance electrically erasable programmable read-only memory(EEPROM) complex programmable logic device(CPLD) ATF1504AS, using which an ESCC algorithm has been proposed. The source code was written in C language. The algorithm of work was written using the dew-point table. This system not only clears the condensation on the glass but also averts condensation. The designed ESCC system begins working once the input information comes close to the dew-point table information. This device enables a wider field of view, thereby increasing safety.

• Journal of Society of Preventive Korean Medicine
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• v.7 no.2
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• pp.35-44
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• 2003

Research papers must be expression given by letter that had fixed types, rules and universal sentence languages to inform many persons about study results until present when these research paper was considered review, oriental medical papers had some problems, as like difficult contents not to inform absolutely, usage of past language, not considerable in logic history and continuity, and have used not fixed types and rules, error of statistical analysis and research construction. Also centered clinic that had trends important treat tools by drugs ,acupuncture and moxa studies. In briefly, papers of korea traditional medicine had some several problems. Oriental medicine has very concerns not only korean but other countries in present and then it will increases much more study in future. For the purpose cope with this concerns korea traditional medicine researchers need much educations of relation department and must recognized much concerns.

• Journal of the Korean Society for Library and Information Science
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• v.6
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• pp.53-70
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• 1979

This is to report the objectives, planning and the process of the establishment of an on-line information retrieval system in Korea. The model is the case of the Library of the Korea Institute of Science and Technology (KIST) which is the multi-disciplinary contract research organization in science and technology. The report explains the objectives and the step by step process such as input materials, analysis of the materials, structure of the data base files, indexes, command language, and the process, technique and logic of information retrieval. A brief comparison is made with other systems such as OCLC and BALLOTS and the authors gave various illustrations and samples to clarify the processes. The authors regrets that they could not give any detailed information on the budget or the cost accrued so far.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.90-94
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• 1987

A structured user-friendly procedures which enable users to program in GRAFCET form directly from sequence specifications have been developed. Using these procedures, we can program the programmable logic controller (PLC) in sequential control and realize programming, debugging, and real-time monitoring. GRAFCET has many advantages like parallelism expression, so we can expect higher productivity and easier maintenance than boolean language or relay-ladder diagram specification when adapts them to PLC.