• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.140-151
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• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1101-1107
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• 2004

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.

• ETRI Journal
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• v.43 no.4
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• pp.728-745
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• 2021

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.274-277
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• 1999

The paper describes a implementation of space vector pulse-width modulation (SVPWM) voltage source inverter using Field Programmable Gate Array(FPGA) for a induction motor control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QL16X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed FPGA for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance voltage source inverter drives. Simulation and Implementation results are shown to verify the usefulness of FPGA as a Application Specific Integrated Circuit(ASIC) in power electronics applications

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.1-9
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• 1994

This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.

• Journal of the Korean Society of Industry Convergence
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• v.2 no.2
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• pp.103-108
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• 1999

The paper describes a implementation of space vector pulse-width modulation voltage source inverter and interfacing of DSP using field programmable gate array(FPGA) for a induction motor vector control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QLl6X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed Application Specific Integrated Circuit(ASIC) for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance induction motor drives with a voltage source inverter. Simulation and implementation results are shown to verify the usefulness of ASIC in a motor drive system and power electronics applications.

• ETRI Journal
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• v.36 no.1
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.603-610
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• 1995

In this paper, we present a highly efficient simulation package which supports simulation from functional level to gate level. The package consists of a set of front-end tools, a logic simulator, named HSIM(Highly efficient logic SIMulator), and an waveform analyzer. The front-end tools include a netlist compiler, functional primitive compiler and behavioral compiler. Key feature of developed simulator is that the compiled behavioral models written in C language are directly executed in the simulation engine using incremental loader. By doing so, we achieved significant speed up as compared with the interpretive functional simulator. Experimental results show that HSIM runs about 55% faster than traditional unit-delay event-driven interpretive simulator.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.622-634
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• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.917-925
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• 2016

Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.