• Proceedings of the KIEE Conference
• /
• 2000.11d
• /
• pp.778-780
• /
• 2000

The 74181 is arithmetic logic units(ALU)/function generator. This circuit performs 16 binary arithmetic operations on two 4-bit words. And a full carry look-ahead scheme is made available in this device. The 74181 can also be utilized as a comparator. This circuit has been also designed to provide 16 possible functions of two Boolean variables without the use of external circuitry. This paper analyzes the function of the logic and the implementation adopted in the design of 74181. The understanding of the logic characteristics of this chip enables us to improve future applications.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.581-582
• /
• 2008

This paper describes novel bootstrapped CMOS differential logic family operating at near-Vth supply voltage. The proposed logic family provides improved switching speed by utilizing voltage bootstrapping for the supply voltage approaching device thresholds. The circuit is configured as differential structure having single bootstrapping capacitor, minimizing area overhead and providing complete logic composition capability. A 64-bit adder designed using the proposed technique in a 0.18um CMOS process provides up to 79% improvement in terms of power-delay product as compared to the conventional adder designed with DCVS.

• Journal of Biosystems Engineering
• /
• v.25 no.1
• /
• pp.63-70
• /
• 2000

In Korea, researches for year-round leaf vegetables production system are in progress and the most of them are focused on environment control. Automation technologies for harvesting , transporting and grading need to be developed. This study was conducted to develop harvesting process automation system profitable to a competitive price. 1. Manipulator and end-effector are to be designed and fabricated , and fuzzy logic controller for controlling these are to be composed. 2. The entire system constructed is to be evaluated through a performance test. A robot system for harvesting a lettuce was developed. It was composed of a manipulator with 20DOF (degrees of freedom) an end-effector, a lettuce feeding conveyor , an air blower , a machine vision device, 6 photoelectric sensors and a fuzzy logic controller. A fuzzy logic control was applied to determined appropriate grip force on lettuce. Leaf area index and height index were used as input parameters, and voltage was used as output parameter for the fuzzy logic controller . Success rate of the lettuce harvesting system was 93.06% , and average harvesting time was about 5 seconds per lettuce.

• Progress in Superconductivity
• /
• v.9 no.2
• /
• pp.157-161
• /
• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.971-974
• /
• 2005

In this paper, we describe photonic sensor interface in SOPC(System on a programmable chip) platform. This platform uses device that has ARM922T processor and APEX FPGA area on a chip. We use two development kits. The one is embedded kit that using Intel's Xscale device, the another is SOPC kit that using Altera's Excalibur device. We implement some device logic that DMAC, ADCC, etc. and application.

• Proceedings of the Korean Magnestics Society Conference
• /
• 2014.11a
• /
• pp.131-131
• /
• 2014

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 1999.10a
• /
• pp.79-80
• /
• 1999

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.3
• /
• pp.146-153
• /
• 2006

We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

• The Magazine of the IEIE
• /
• v.37 no.8
• /
• pp.50-59
• /
• 2010

$0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.

• Journal of the Korea Society of Computer and Information
• /
• v.23 no.8
• /
• pp.95-99
• /
• 2018

This research is related to GPS(global positioning system) enabled device navigation service and consists of two parts. The first is the logic that records the route guidance video and records GPS information in time, and the second is the logic that outputs the created video data based on real time GPS. The recording logic first determines the origin and destination, records the video from the origin to the destination and it adjusts the speed of the image in a specific area so that the user can see it easily. And insert ancillary information and advertisements that can help guide the route. In the output logic, we provide navigation services using the video and GPS data tables we created, and it receives user's GPS information in real time and corrects it based on the recent user location to reduce errors. This provides local guidance services to people who lack language skills like foreigners.