• Title/Summary/Keyword: logic device

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Systematic Elicitation of Proximity for Context Management

  • Kim Chang-Suk;Lee Sang-Yong;Son Dong-Cheul
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • 제6권2호
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    • pp.167-172
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    • 2006
  • As ubiquitous devices are fast spreading, the communication problem between humans and these devices is on the rise. The use of context is important in interactive application such as handhold and ubiquitous computing. Context is not crisp data, so it is necessary to introduce the fuzzy concept. The proxity relation is represented by the degree of closeness or similarity between data objects of a scalar domain. A context manager of context-awareness system evaluates imprecise queries with the proximity relations. in this paper, a systematic proximity elicitation method are proposed. The proposed generation method is simple and systematic. It is based on the well-known fuzzy set theory and applicable to the real world applications because it has tuning parameter and weighting factor. The proposed representations of proximity relation is more efficient than the ordinary matrix representation since it reflects some properties of a proximity relation to save space. We show an experiments of quantitative calculate for the proximity relation. And we analyze the time complexity and the space occupancy of the proposed representation method.

Data Compression Algorithm for Efficient Data Transmission in Digital Optical Repeaters

  • Kim, Jae Wan;Eom, Doo Seop
    • 전자공학회논문지
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    • 제49권12호
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    • pp.142-146
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    • 2012
  • Today, the demand for high-speed data communication and mobile communication has exploded. Thus, there is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication with these characteristics consists of a master unit (MU) and a slave unit (SU). However, the digital optical units that are currently commercialized or being developed transmit data without compression. Thus, digital optical communication using these units is restricted by the quantity of optical frames when adding diversity or operating with various combinations of CDMA, WCDMA, WiBro, GSM, LTE, and other mobile communication technologies. This paper suggests the application of a data compression algorithm to a digital signal processor (DSP) chip as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD) of a digital optical unit to add separate optical waves or to transmit complex data without specific changes in design of the optical frame.

아날로그/디지탈 회로 구성에 쓰이는 BCDMOS소자의 제작에 관한 연구 (A Study on the Analog/Digital BCDMOS Technology)

  • 박치선
    • 대한전자공학회논문지
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    • 제26권1호
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    • pp.62-68
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    • 1989
  • 본 논문에서는 아날로그/디지탈 회로 구성시 입출력부는 바이폴라 소자로 내부의 논리회로 부분은 CMOS 소자로 높은 내압을 요구하는 부분에는 DMOS 소자를 이용할 수 있는, BCDMOS 공정 기술개발을 하고자 하였다. BCDMOS 제작 공정은 폴리게이트 p-well CMOS 공정을 기본으로 하였고, 소자설계의 기본개념은 공정흐름을 복잡하지 않게 하면서 바이폴라, CMOS, DMOS 소자 각각의 특성을 좋게하는데 두었다. 실험결과로서 바이폴라 npn 트랜지스터의 $h_{FE}$ 특성은 320(Ib-$10{\mu}A$)정도이며, CMOS 소자에서는 n-채자에서는 항복전압이 115V이상의 특성을 얻을 수 있었다.

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DESIGN CONCEPT FOR SINGLE CHIP MOSAIC CCD CONTROLLER

  • HAN WONYONG;JIN Ho;WALKER DAVID D.;CLAYTON MARTIN
    • 천문학회지
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    • 제29권spc1호
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    • pp.389-390
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    • 1996
  • The CCDs are widely used in astronomical observations either in direct imaging use or spectroscopic mode. However, the areas of available sensors are too small for large imaging format. One possibility to obtain large detection area is to assemble mosaics of CCD, and drive them simultaneously. Parallel driving of many CCDs together rules out the possibility of individual tuning; however, such optimisation is very important, when the ultimate low light level performance is required, particularly for new, or mixed devices. In this work, a new concept is explored for an entirely novel approach, where the drive waveforms are multiplexed and interleaved. This simultaneously reduces the number of leadout connections and permits individual optimisation efficiently. The digital controller can be designed within a single EPLD (Erasable Programmable Logic Device) chip produced by a CAD software package, where most of the digital controller circuits are integrated. This method can minimise the component. count., and improve the system efficiency greatly, based on earlier works by Han et a1. (1996, 1994). The system software has an open architecture to permit convenient modification by the user, to fit their specific purposes. Some variable system control parameters can be selected by a user with a wider range of choice. The digital controller design concept allows great flexibility of system parameters by the software, specifically for the compatibility to deal with any number of mixed CCDs, and in any format, within the practical limit.

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An 8-b 1GS/s Fractional Folding CMOS Analog-to-Digital Converter with an Arithmetic Digital Encoding Technique

  • Lee, Seongjoo;Lee, Jangwoo;Lee, Mun-Kyo;Nah, Sun-Phil;Song, Minkyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권5호
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    • pp.473-481
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    • 2013
  • A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

Effect of Filter Parameters on a Supercontinuum-Based All-Optical Tunable Thresholder

  • Zhu, Huatao;Wang, Rong;Pu, Tao;Fang, Tao;Xiang, Peng;Zhu, Huihui
    • Journal of the Optical Society of Korea
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    • 제20권4호
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    • pp.470-475
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    • 2016
  • In this paper, the effects of filter parameters on a supercontinuum-based all-optical thresholder are experimentally investigated. By tuning the filter parameters, the power transfer function and power transmission function are tailored. The experimental results show that a thresholder with short center wavelength has a better power function, and the slope in the middle level of the thresholder increases with increasing bandwidth. Through tuning the filter parameters, the thresholder can achieve a steplike power transfer function for optical thresholding, and a steplike power transmission function for optical self-switching. This makes the supercontinuum-based thresholder more flexible, and allows customization of performance to meet different demands in various applications.

유연 구조물의 진동제어를 위한 선형모터댐퍼 (Linear Motor Damper for Vibration Control of Flexible Structure)

  • 강호식;송오섭;김영찬;김두훈;심상덕
    • 한국소음진동공학회논문집
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    • 제15권4호
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    • pp.492-498
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    • 2005
  • A linear motor damper based on the linear motor principle is developed to suppress structural vibration. This paper deals with the design, analysis, and manufacture of the linear motor damper. It is designed to be able to move the auxiliary mass of 1500kg, up to $\pm250mm$ stroke. The control algorithm was designed based on LQG control logic with acceleration feedback. Through performance tests, it was confirmed that the developed hybrid mass damper has reliable feasibility as a control device for structural control. In addition, the linear motor damper is more economical than both hydraulic and electric motor driving mass damper with respect to simple structure and low maintenance cost. A series of performance tests of the linear motor damper system were carried out on the full-scale steel frame structure in UNISON Corporation. Through the performance tests, it was confirmed that acceleration levels are reduced down 10dB for first mode of structure

SINGLE ERROR CORRECTING CODE USING PBCA

  • Cho, Sung-Jin;Kim, Han-Doo;Pyo, Yong-Soo;Park, Yong-Bum;Hwang, Yoon-Hee;Choi, Un-Sook;Heo, Seong-Hun
    • Journal of applied mathematics & informatics
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    • 제14권1_2호
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    • pp.461-471
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    • 2004
  • In recent years, large volumes of data are transferred between a computer system and various subsystems through digital logic circuits and interconnected wires. And there always exist potential errors when data are transferred due to electrical noise, device malfunction, or even timing errors. In general, parity checking circuits are usually employed for detection of single-bit errors. However, it is not sufficient to enhance system reliability and availability for efficient error detection. It is necessary to detect and further correct errors up to a certain level within the affordable cost. In this paper, we report a generation of 3-distance code using the characteristic matrix of a PBCA.

Smart Diesel Generator Control System

  • Jeong, Yunju;Ansari, Md Israfil;Shin, WooHyeon;Kang, Bonggu;Shim, Jaechang
    • 한국멀티미디어학회논문지
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    • 제20권2호
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    • pp.271-278
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    • 2017
  • This paper introduces a user-friendly PLC (programmable logic controller) monitoring and control system of heavy machinery using Android based smartphone. The proposed system will control diesel generator and many such like machine without a dedicated PC with respect to similar system and offers a new communication protocol for handling it. The smartphone controls the generator via Wi-Fi, through which it connects to the Raspberry pi which will be installed in the PLC panel to setup the communication between them. Furthermore, Raspberry pi connects to two devices, one is PLC which gives the status and current information of the machine and to ON/OFF the machine. This proposed system used RS485 as a key mediator for data exchanging between Raspberry PI(master) and PLC(slave). RS485 allows multiple devices (up to 32) to communicate at half duplex on single pair of wires and provides a long connectivity area (up to 1200 meters) as compared to another device. This proposed system specially focused on accurate data flow between smartphone and PLC panel.

FPGA를 이용한 멀티레벨 스위칭 함수 구현 방법 (Method of Multi-level Switching Function based on FPGA)

  • 이화춘;송지석;박성준;이민중
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2008년도 추계종합학술대회 B
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    • pp.195-198
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    • 2008
  • 최근 태양광 발전시스템 등 낮은 전압을 발생하는 전원소스를 이용하여 높은 승압효과를 얻기 위한 멀티레벨 인버터에 대한 관심이 높아지고 있다. 본 논문은 FPGA 기반 멀티레벨 인버터용 스위칭 함수를 구현하고자 한다. FPGA는 프로그램 가능한 로직 디바이스로써 풀 디지털 스위칭함수를 구현하는 효율적이다. 본 논문에서는 FPGA 기반 스위칭 함수를 구현하기 위해서 마이크로프로세서로부터 출력되는 클럭과 동기신호로 독립적으로 구동이 되도록 하였다.

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