• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.747-752
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• 2014

This paper relates 10% shrink from $0.13{\mu}m$ design for logic devices as well as input and output (I/O) circuits, different from the previous shrink methodologies which shrink only core device. Thin gate oxide was changed to decoupled plasma nitridation(DPN) oxide as a thin gate oxide (1.2V) to reduce the flicker noise, resulting in three to five times lower flicker noise than pre-shrink process. Unavoidable issue by shrink is capacitor for this normally metal insulator metal (MIM). To solve this issue, 20% higher unit MIM capacitor ($1.2fF/{\mu}m^2$) was developed and its performance were evaluated.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.365-370
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• 2004

The integration of intelligent devices, devices-level networks, and software into motor control systems can deliver improved diagnostics, fast warnings for increased system reliability, design flexibility, and simplified wiring. Remote access to motor-control information also affords an opportunity for reduced exposure to hazardous voltage and improved personnel safety during startup and trouble-shooting. This paper presents LonWorks fieldbus networked intelligent induction control system architecture. Experimental bed system with two inverter motor driving system for controlling 1.5kW induction motor is configured for LonWorks networked intelligent motor control. In recent years, MCCs have evolved to include component technologies, such as variable-speed drives, solid-state starters, and electronic overload relays. Integration was accomplished through hardwiring to a programmable logic controller (PLC) or distributed control system (DCS). Devicelevel communication networks brought new possibilities for advanced monitoring, control and diagnostics. This LonWorks network offered the opportunity for greatly simplified wiring, eliminating the bundles of control interwiring and corresponding complex interwiring diagrams. An intelligent MCC connected in device level control network proves users with significant new information for preventing or minimizing downtime. This information includes warnings of abnormal operation, identification of trip causes, automated logging of events, and electronic documentation. In order to show the application of the multi-motors control system, the prototype control system is implemented. This paper is the first step to drive multi-motors with serial communication which can satisfy the real time operation using LonWorks network.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.2
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• pp.179-184
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• 2010

The digital substation automation system has contributed hugely to increasing the stability of power systems by providing not only protection and control of power systems but diagnostic features alongside them. Digital substation automation systems in the scale of substations consist of integrated operation systems and intelligent electronic devices. The main intelligent electronic devices currently in use are digital protection relays and the bay controllers in Gas insulated switchgears. Proficiently accomplishing the coordination of protection within the power system as a means of ensuring reliability and contriving for the stability of power supply through connection of function, the application of bay controllers is crucial, which collectively manage the protection relay at the bay level in order to achieve both. In this research, the bay controllers to be used in high-voltage Gas insulated switchgear has been localized, and in particular, the logic function and editor required in order to minimize the complicated hardware-like cable connections in the local panel have been developed. In addition, to ensure the strength and reliability of the bay controller hardware developed herein, the type tests from KERI have been successfully completed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.3
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• pp.43-48
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• 2000

In this paper, CPLD(Complex Programmable Logic Device) controller designed with VHDL is developed. With the controller, the harmonics from 3 phase diode rectifier are suppressed and power factor is also improved. The input current of diode rectifier is drawn from the ac mains only during the period in the ac cycle when the instantaneous voltage is greater than the voltage across the dc-link capacitor. The three bidirectional switches rated at very small power are installed in a conventional three phase diode rectifier. Using CPLD controller, an idle current charges to capacitors continuously. Results of simulation and experimental demonstrate a reduction of harmonics, a improvement of power factor and THD.

• Proceedings of the KOSOMBE Conference
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• v.1997 no.05
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• pp.64-67
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• 1997

In the total artificial heart(TAH), a transcutaneous information transmission system(TITS) is vely important to monitor the TAH status and detect the device failure, and repair the possible problems. First of all, the communication channel(skin) and method were simulated in terms of transmittance, scattering, reflection and absorption, then the system was designed with size reduction including low power consumption and reliability compared to the previous one. The informations are transmitted through the skin(approximately 1cm in depth) by frequency modulated near infrared(NIR) pulses using 780nm laser diodes as transmitters and photodiode as receiver with high speed and high spectral sensitivity. The logic high and low frequencies are 3MHz, 1MHz respectively. The system is a bidirectional data link for more than 38.4Kbps data rate, full-duplex with a bit error rate of less than $10^{-5}$.

• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.490-495
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• 1999

In 0.18 $\mu \textrm m$ LOGIC device, the etch rate of NMOS polysilicons is different from that of PMOS polysilicons due to the state of polysilicon to manufacture gate line. To control the etch profile, we tested the ratio of $Cl_2$/HBr gas and the total chamber pressure, and also we reduced Back He pressure to get the vertical profile. In the case of manufacturing the gate photoresist line, we used Bottom Anti-Reflective Coating (BARC) to protect refrection of light. As a result we found that $CF_4O_2$ gas is good to etch BARC, because of high selectivity and good photoresist line profile after etching BARC. in the results of the characterization of plasma damage to the antenna effect of gate oxide, NO type thin film(growing gate oxide in 0, ambient followed by an NO anneal) is better than wet type thin film(growing gate oxide in $0_2+H_2$ ambient).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.60-64
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• 2007

In this paper, we designed FFT for European DTV and implemented system with Stratix EP1S25F672C6 FPGA At the implemented FFT, we used SIC architecture. SIC architecture is composed of algorithm-specific processing element, RAM memory, registers, and a central or distributed control unit. Designed FFT was acceptable either 2K or 8K point FFT processing, and is selectable guard interval such as 1/4, 1/8, 1/16, 1/32. Consequently, it was suitable for the standard of DVB-T(Digital Terrestrial Video Transmission System) specification. It resulted in 12% of total logic gate and 53% of total memory bit in Stratix device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.107-116
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• 2012

In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method to optimize the operating frequency, band-width as well as power consumption is proposed. This method is based on bipolar device characteristics, whereby a negative resistance model can be used to estimate the optimal normalized upper frequency and lower frequency of frequency dividers under different conditions, which is conventionally ignored in literatures. This method provides a simple but efficient procedure in designing high performance frequency dividers for different applications. To verify the proposed method, a static divide-by-2 at millimeter wave ranges is implemented in 180 nm SiGe technology. Measurement results of the divider demonstrate significant improvement in the figure of merit as compared with literatures.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.5
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• pp.105-111
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• 2010

In this paper the elasticity of fault-detection algorithm based on fuzzy logic is proposed through lots of experiments, justifying its validity. The four mathematical morpholgical operators was defined to detect the cracks. The cracks was detected via center of area method with ${\lambda}$-fuzzy measure of fuzzy sets. However generally favorable, the result owes to how adequate the lighting device is designed in case of the so far fine crack of pieces. In an attempt to improve the response of the system, It is designed to minimize the use of memory via LookUp table in software.