• Title/Summary/Keyword: logic device

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Integration of SoC Test and Verification Using Embedded Processor and Reconfigurable Architecture (임베디드 프로세서와 재구성 가능한 구조를 이용한 SoC 테스트와 검증의 통합)

  • Kim Nam-Sub;Cho Won-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.7 s.349
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    • pp.38-49
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    • 2006
  • In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

Effects of the electronic expansion valve and variable velocity compressor on the performance of a refrigeration system

  • Lago, Taynara G.S.;Ismail, Kamal A.R.;Nobrega, Claudia R.E.S.;Moura, Luiz F.M.
    • Advances in Energy Research
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    • v.7 no.1
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    • pp.1-19
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    • 2020
  • Energy consumption of air-conditioning and refrigeration systems is responsible for about 25 to 30% of the energy demand especially in hot seasons. This equipment is mostly electricity dependent and their use in principle affects negatively the environment. Enhancing the energy efficiency of the existing equipment is important as one of the measures to reduce environment impacts. This paper reports the results of an experimental study to evaluate the impacts of the use electronic expansion valve and variable velocity compressor on the performance of vapor compression refrigeration system. The experimental rig is composed of two independent circuits one for the vapor compression system and the other is the secondary fluid system. The vapor compression system is composed of a forced air condenser unit, evaporator, hermetic compressor and expansion elements, while the secondary system has a pump for circulating the secondary fluid, and an air conditioning heat exchanger. The manufacturer's data was used to determine the optimal points of operation of the system and consequently tests were done to evaluate the influence of variation of the compressor velocity and the opening of the expansion device on the performance of the refrigeration system. A fuzzy logic model was developed to control the rotational velocity of the compressor and the thermal load. Fuzzy control model was made in LabVIEW software with the objective of improving the system performance, stability and energy saving. The results showed that the use of fuzzy logic as a form of control strategy resulted in a better energy efficiency.

PLD implementation of the N-D digital filter with VHDL (VHDL을 이용한 다차원 디지털 필터의 PLD 구현)

  • Jeong, Jae-Gil
    • The Journal of Engineering Research
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    • v.6 no.1
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    • pp.111-124
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    • 2004
  • The advanced semiconductor technology and electronic design automation(EDA) tools make it possible to implement the system on the programmable logic devices. The electronic design method is also changing from schematic capture to hardware description language. In this paper, I present the architecture of multi-dimensional digital filter which can be efficiently implemented on PLDs. This is based on the former research results which are called algorithm decomposition technique. Algorithm decomposition technique is used to obtain the computational primitive from the state space equations of the multi-dimensional digital filtering algorithm. The obtained computational primitive is designed with VHDL. This can be used to implement the filtering system as a component. The designed filtering system is implemented on the PLD. Therefore, the filter can be upgradable on system. It is greatly reduced the time-to-market time of the system that is based on the multi-dimensional filter.

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Vulnerability Case Analysis of the High Power Electromagnetic Pulse on Digital Control System (디지털 제어장치의 고출력 전자기펄스에 대한 취약성 사례 분석)

  • Woo, Jeong Min;Ju, Mun-No;Lee, Hong-Sik;Kang, Sung-Man;Choi, Seung-Kyu;Lee, Jae-Bok
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.9
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    • pp.698-706
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    • 2017
  • The risk of high power electromagnetic(HPEM) pulse exposure to the devices used in digital control system such as PLC(programmable logic controller) and communication cable is increasing. In this paper, two different frequency ranges HPEMs were exposed to those control systems to assess the each vulnerability. The vulnerability of the EUTs exposed from HPEM were analyzed and compared with a variation of distances and source power. As the EUTs were exposed to higher level of HPEM, the voltage and communication waveform of the control system had shown a distorted response. And the unshielded twisted pair(UTP) cable connected to the EUTs showed operation failures with induced voltage. However, the foiled twisted pair(FTP) cable shielded the connected device efficiently from the HPEM exposure. Therefore, the necessity of the protection measures against the vulnerability of HPEM exposure for the digital control system used in power facilities and industrial site were verified.

A Study on the Optical Bistable Characteristic of a Multi-Section DFB-LD (다전극 DFB-LD의 광 쌍안정 특성에 관한 연구)

  • Kim, Geun-Cheol;Jeong, Yeong-Cheol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.8
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    • pp.1-11
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    • 2002
  • A multi-section DFB-LD shows optical bistability subject to externally injected light signal, then it has potential applications such as wavelength conversion and optical logic gates. In this paper, we have studied the optical bistability in multi-section DFB-LD using split-step time-domain model. It is confirmed that the multi-section DFB-LD, which is excited inhomogeneously, shows bistability. The optical bistable characteristics are investigated when input light is injected into a absorptive region. Simulation results show that multi-section DFB-LD works as a flip-flop depending on the set-reset optical pulse which has a few ns in switching time and a few pj in switching energy, so that it can act as a optical logic device. Besides, if we change the carrier lifetime and the differential gain coefficient, it is expected that the response time of optical output signal can be reduced.

A Method to Improve Energy Efficiency for IoT Using SSL/TLS on Wireless Network (무선 환경에서 SSL/TLS를 사용하는 IoT의 에너지 효율성 향상을 위한 기법)

  • Chung, Jin Hee;Cho, Tae Ho
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.26 no.3
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    • pp.661-666
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    • 2016
  • The Internet of Things (IoT) is an infrastructure of physical objects that could be connected to the Internet. Most of these are low performance to ensure a reasonable cost for the smart physical objects. Thus, these devices usually use a lightweight messaging protocol: message queue telemetry transport with SSL/TLS. Cipher suites in device are fixed by default and selected based on preference in SSL/TLS. However, the selected cipher suite provides high security level more than expected. This limitation causes energy waste and overhead of devices. In order to counter this problem, we proposed fuzzy logic based cipher suite decision method to improve energy efficiency. Our proposed method saved 36.03% energy.

A Local Tuning Scheme of RED using Genetic Algorithm for Efficient Network Management in Muti-Core CPU Environment (멀티코어 CPU 환경하에서 능률적인 네트워크 관리를 위한 유전알고리즘을 이용한 국부적 RED 조정 기법)

  • Song, Ja-Young;Choe, Byeong-Seog
    • Journal of Internet Computing and Services
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    • v.11 no.1
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    • pp.1-13
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    • 2010
  • It is not easy to set RED(Random Early Detection) parameter according to environment in managing Network Device. Especially, it is more difficult to set parameter in the case of maintaining the constant service rate according to the change of environment. In this paper, we hypothesize the router that has Multi-core CPU in output queue and propose AI RED(Artificial Intelligence RED), which directly induces Genetic Algorithm of Artificial Intelligence in the output queue that is appropriate to the optimization of parameter according to RED environment, which is automatically adaptive to workload. As a result, AI RED Is simpler and finer than FuRED(Fuzzy-Logic-based RED), and RED parameter that AI RED searches through simulations is more adaptive to environment than standard RED parameter, providing the effective service. Consequently, the automation of management of RED parameter can provide a manager with the enhancement of efficiency in Network management.

Design of Optimized ARIA Crypto-Processor Using Composite Field S-Box (합성체 S-Box 기반 최적의 ARIA 암호프로세서 설계)

  • Kang, Min Sup
    • KIPS Transactions on Computer and Communication Systems
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    • v.8 no.11
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    • pp.271-276
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    • 2019
  • Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

Experimental Evaluation of Seismic Response Control Performance of Smart TMD (스마트 TMD의 지진응답 제어성능 실험적 검토)

  • Kang, Joo-Won;Kim, Hyun-Su
    • Journal of Korean Association for Spatial Structures
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    • v.22 no.3
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    • pp.49-56
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    • 2022
  • Tuned mass damper (TMD) is widely used to reduce dynamic responses of structures subjected to earthquake loads. A smart tuned mass damper (STMD) was proposed to increase control performance of a traditional passive TMD. A lot of research was conducted to investigate the control performance of a STMD based on analytical method. Experimental study of evaluation of control performance of a STMD was not widely conducted to date. Therefore, seismic response reduction capacity of a STMD was experimentally investigated in this study. For this purpose, a STMD was manufactured using an MR (magnetorheological) damper. A simple structure presenting dynamic characteristics of spacial roof structure was made as a test structure. A STMD was made to control vertical responses of the test structure. Two artificial ground motions and a resonance harmonic load were selected as experimental seismic excitations. Shaking table test was conducted to evaluate control performance of a STMD. Control algorithms are one of main factors affect control performance of a STMD. In this study, a groundhook algorithm that is a traditional semi-active control algorithm was selected. And fuzzy logic controller (FLC) was used to control a STMD. The FLC was optimized by multi-objective genetic algorithm. The experimental results presented that the TMD can effectively reduce seismic responses of the example structures subjected to various excitations. It was also experimentally shown that the STMD can more effectively reduce seismic responses of the example structures conpared to the passive TMD.

Modeling and Simulation Analysis of the Setup Reduction Method in Automobile Painting Process (자동차 도장 공정의 셋업 감소 방법 모델링 및 시뮬레이션 분석)

  • Han, Yong-Hee
    • Journal of the Korea Society for Simulation
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    • v.18 no.3
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    • pp.147-154
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    • 2009
  • In this study we investigate the problem of reducing color change cost at painting operations in an automobile assembly plant. Changing control logic at conveyor junction points prior to the top coat line has been proposed and analyzed using the discrete event simulation model we developed using AutoMod. We also discussed the project which initiated this research as well as the details of painting operations. Simulation analysis showed that the grouping ratio increases from 1.8 to 2.5 if the proposed control logic change is applied to the plant. Contrary to other approaches such as using dedicated equipment for resequencing, our approach has the merit of less investment cost, no need for additional space consumption. We finally note that the grouping ratio can be further increased if our algorithms is implemented as well as CRS (Color Rescheduling Storage) is installed.