• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2002년도 춘계학술발표논문집
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• pp.215-217
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• 2002

본 논문에서는 CM-MVL(Current Mode Multi-Valued Logic)을 이용한 Host와 LCD Controller 간에 인터페이스 회로를 제안한다. 제안한 회로는 기존의 LVDS(Low Voltage Differential Signaling)과 TMDS(Transition Minimized Differential Signaling)와 같은 전류 특성을 가지며, 3비트 동시 전송이 가능하여 동일한 전송 속도 하에서 보다 많은 데이터를 전송할 수 있다. 그리고 전류에 의한 데이터 전송을 통하여 노이즈에 강한 특성을 나타낸다. 제안한 회로는 HSPICE 시뮬레이션을 통해서 회로의 동작을 확인하였다.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2009년도 추계학술발표논문집
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• pp.636-639
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• 2009

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.418-421
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• 1988

Elevator system requires position and speed control at the same time recently. The control device of existing Elevator system making hardware is simplified by using micro-processor that have been developed. In this papers, it consists of contactless logic circuit using miro-processor and digital components. This paper shows that as this system control voltage and frequency using PWM inverter at the same time, speed control is accurate, acceleration and deceleration is soft and passengers can be feel comfortably because speed change is a little during driving.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.753-756
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• 1999

In this research we designed and synthesized an effective Synchronous DRAM controller for Interleaved Column Mode Access with VHDL. When target device was ALTERA CPLD MA$\times$712 105 logic cells were used. The result of the simulation at 66MHz clock operation, the clock-to-output time t$_{co}$ was 4.5㎱ and the SDRAM controller was in good working order.r. good working order.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.687-688
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• 2006

This paper presents implementation of the lifting based DWT processor interface which the process of JPEG2000. The proposed architecture uses Excalibur device produced Altera. This study describes CIS(CMOS Image Sensor), DMA(Direct Memory Access) and DWT control logic

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2015년도 자성 및 자성재료 국제학술대회
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• pp.95-95
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• 2015

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2000년도 하계종합학술대회논문집
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• pp.341-344
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• 2000

The 0-1 knapsack processor performing dynamic programming is designed and implemented on a programmable logic device. Three types of a processor, each with different behavioral models, are presented, and the operation of a processor of each type is verified with an instance of the 0-1 knapsack problem.

• Journal of Power Electronics
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• 제15권3호
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• pp.830-840
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• 2015

The H-bridge inverter is the fundamental power cell of the cascaded distribution static synchronous compensator (DSTATCOM). Thus, cell reliability is important to the compensation performance and stability of the overall system. The concept of the power electronics building block (PEBB) is an ideal solution for the power cell design. In this paper, an H-bridge inverter-based “plug and play” HPEBB is introduced into the main circuit and the controller to improve the compensation performance and reliability of the device. The section that discusses the main circuit primarily emphasizes the design of electrical parameters, physical structure, and thermal dissipation. The section that presents the controller part focuses on the principle of complex programmable logic device -based universal controller This section also analyzes typical reliability and anti-interference issues. The function and reliability of HPEBB are verified by experiments that are conducted on an HPEBB test-bed and on a 10 kV/± 10 Mvar DSTATCOM industrial prototype.

• ETRI Journal
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• 제32권2호
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• pp.319-326
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• 2010

Photonics offers a solution to data communication between logic devices in computing systems; however, the integration of photonic components into electronic chips is rather limited due to their size incompatibility. Dimensions of photonic components are therefore being forced to be scaled down dramatically to achieve a much higher system performance. To integrate these nano-photonic components, surface plasmon-polaritons and/or energy transfer mechanisms are used to form plasmonic chips. In this paper, the operating principle of plasmonic waveguide devices is reviewed within the mid-infrared spectral region at the 2 ${\mu}m$ to 5 ${\mu}m$ range, including lossless signal propagation by introducing gain. Experimental results demonstrate that these plasmonic devices, of sizes approximately half of the operating free-space wavelengths, require less gain to achieve lossless propagation. Through optimization of device performance by means of methods such as the use of new plasmonic waveguide materials that exhibit a much lower minimal loss value, these plasmonic devices can significantly impact electronic systems used in data communications, signal processing, and sensors industries.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.482-491
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• 2012

In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.